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US5392248A
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Circuit and method for detecting column-line shorts in integrated-circuit memories
Assignee: Texas Instruments Inc
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Filing: 1993-10-26
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Granted: 1995-02-21
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Expires: 2013-10-26
Abstract
Abstract The column-line short detection circuit of this invention includes a special test circuit that turns off wordlines (15), a N-channel transistor (23) for each column line (18), a decoder (19a) that uses only the least significant column address (20d) for input to the test circuit, and a sensor (SA) to detect current between shorted column lines (18). Because the column-line short detection circuit of this invention uses only the least significant address as input for column decoder (19a), it requires a very small number of transistors.
Inventors
- 👤 Phat C. Truong
- 👤 Tim M. Coffman
- 👤 Sung-Wei Lin
- 👤 T. Damodar Reddy
- 👤 Dennis R. Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:22
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/025; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/50; G11C16/00; G11C16/02; G11C16/04; G11C2029/5006
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
112 words
A method for detecting shorts between parallel column lines of a memory array, said parallel column lines including alternate column lines and other alternate column lines, said memory array including wordlines, column address inputs and a reference-potential, said method comprising: connecting said reference-potential to each of said wordlines; coupling said alternate column lines to a sensing circuit, coupling said other alternate column lines to said reference-potential; and with said wordlines at said reference potential and with said alternate column lines and said other alternate column lines coupled to said sensing circuit and to said reference-potential, sensing the resistance to current flow between said alternate column lines and said other alternate column lines.
Claim 2
Independent Claim
112 words
A method for detecting shorts between parallel column lines of a memory array, said parallel column lines including alternate column lines and other alternate column lines, said memory array including wordlines, column address inputs and a reference-potential, said method comprising: connecting said reference-potential to each of said wordlines; coupling said alternate column lines to a sensing circuit, coupling said other alternate column lines to said reference-potential; and with said wordlines at said reference potential and with said alternate column lines and said other alternate column lines coupled to said sensing circuit and to said reference-potential, sensing the resistance to current flow between said alternate column lines and said other alternate column lines.
Claim 3
Dependent Claim
14 words
The method of claim 1, wherein said column lines are doped polycrystalline silicon conductors.
Claim 4
Dependent Claim
19 words
The method of claim 1, wherein said other alternate column lines are coupled to said reference-potential by N-channel transistors.
Claim 5
Dependent Claim
13 words
The method of claim 1, wherein said sensing circuit is a sense amplifier.
Claim 6
Dependent Claim
17 words
The method of claim 1, wherein said memory array includes rows and columns of floating-gate memory cells.
Claim 7
Dependent Claim
61 words
The method of claim 1, wherein the source-drain path of a transistor couples each said column line to said reference-potential, wherein the gates of those said transistors coupled to said alternate column lines are coupled to a first control electrode, wherein the gates of those said transistors coupled to said other alternate column lines are coupled to a second control electrode.
Claim 8
Dependent Claim
39 words
The method of claim 6, wherein a decoder, in response to a column-address input, couples said first control electrode to said reference-potential and couples said second control electrode to a second voltage different from the voltage at said reference-potential.
Claim 9
Dependent Claim
18 words
The method of claim 1, wherein said wordlines are connected to said reference potential by a wordline decoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-20 | 1998-08-22 | 1999-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-20 | 2002-08-22 | 2003-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-20 | 2006-08-22 | 2007-02-21 | $7700.00 | Window Closed / Lapsed |