Patent US5394355A successfully refreshed from Google Patents.
US5394355A
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Read only memory for storing multi-data
Assignee: Renesas Electronics Corp
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Filing: 1993-08-20
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Granted: 1995-02-28
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Expires: 2013-08-20
Abstract
Abstract A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.
Inventors
- 👤 Shinichi Uramoto
- 👤 Tetsuya Matsumura
- 👤 Masahiko Yoshimoto
- 👤 Kazuya Ishihara
- 👤 Hiroshi Segawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:27
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5692; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5617; G11C2211/563; G11C2211/5634
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
145 words
A read only memory device comprising: at least one bit line for transmitting internal data; a plurality of word lines to which row driving signals are transmitted, respectively; at least three reference potential transmission lines each for transmitting a potential; potential setting means responsive to a potential designating signal for selectively establishing a potential of each of at least two of said at least three reference potential transmission lines; and a plurality of memory cells disposed at respective intersections between said at least one bit line and respective said word lines for respectively storing data, each memory cell including a transistor element for connecting or disconnecting one of said at least three reference potential transmission lines to and from an associated bit line in response to said row driving signal on an associated word line, wherein each memory cell can store multi-data of different addresses.
Claim 2
Dependent Claim
145 words
A read only memory device comprising: at least one bit line for transmitting internal data; a plurality of word lines to which row driving signals are transmitted, respectively; at least three reference potential transmission lines each for transmitting a potential; potential setting means responsive to a potential designating signal for selectively establishing a potential of each of at least two of said at least three reference potential transmission lines; and a plurality of memory cells disposed at respective intersections between said at least one bit line and respective said word lines for respectively storing data, each memory cell including a transistor element for connecting or disconnecting one of said at least three reference potential transmission lines to and from an associated bit line in response to said row driving signal on an associated word line, wherein each memory cell can store multi-data of different addresses.
Claim 3
Dependent Claim
41 words
A read only memory device according to claim 1, wherein said potential setting means includes means for setting the potentials of said at least three reference potential transmission lines in different combinations of potentials in accordance with said potential designating signal.
Claim 4
Dependent Claim
20 words
A read only memory device according to claim 1, wherein each of said memory cells consists of one transistor element.
Claim 5
Dependent Claim
30 words
A read only memory device according to claim 1, wherein said at least three reference potential transmission lines are arranged to be parallel with said at least one bit line.
Claim 6
Dependent Claim
33 words
A read only memory device according to claim 4, wherein said at least three of reference potential transmission lines are arranged to be shared between memory cells provided for two adjacent bit lines.
Claim 7
Dependent Claim
107 words
A memory cell for storing multi-data of different addresses, comprising: a transistor element having a control electrode for receiving a row selection signal, a first conduction terminal for receiving a reference potential and a second conduction terminal for transmitting stored data to an internal data transmission line, said reference potential being selectively established in response to an externally applied potential designating signal, said reference potential determining said stored data in said memory cell and said reference potential established to a first level in a first access cycle for accessing said memory cell and to a second level in a second access cycle for accessing said memory cell.
Claim 8
Dependent Claim
107 words
A memory cell for storing multi-data of different addresses, comprising: a transistor element having a control electrode for receiving a row selection signal, a first conduction terminal for receiving a reference potential and a second conduction terminal for transmitting stored data to an internal data transmission line, said reference potential being selectively established in response to an externally applied potential designating signal, said reference potential determining said stored data in said memory cell and said reference potential established to a first level in a first access cycle for accessing said memory cell and to a second level in a second access cycle for accessing said memory cell.
Claim 9
Dependent Claim
103 words
A memory cell for storing multi-data of different addresses, comprising: a transistor element having a control electrode for receiving a row selection signal, a first conduction terminal having one of either of two states, i. an open state, and ii. receiving a reference potential; and a second conduction terminal for transmitting stored data to an internal data transmission line; said reference potential being selectively established in response to an externally applied potential designating signal to a first level in a first access cycle for accessing said memory cell and to a second level in a second access cycle for accessing said memory cell.
Claim 10
Dependent Claim
103 words
A memory cell for storing multi-data of different addresses, comprising: a transistor element having a control electrode for receiving a row selection signal, a first conduction terminal having one of either of two states, i. an open state, and ii. receiving a reference potential; and a second conduction terminal for transmitting stored data to an internal data transmission line; said reference potential being selectively established in response to an externally applied potential designating signal to a first level in a first access cycle for accessing said memory cell and to a second level in a second access cycle for accessing said memory cell.
Claim 11
Dependent Claim
125 words
A storage element for storing multi-data of different addresses comprising: a first transistor element having a control electrode coupled to receive a first row select signal, a first conduction terminal coupled to a common node and a second conduction terminal coupled to a first internal data transmission line; and a second transistor element having a control electrode coupled to receive a second row select signal generated independently of said first row select signal, a first conduction terminal coupled to the common node, and a second conduction terminal coupled to a second internal data transmission line; said common node coupled to one of at least three reference potential transmitting lines to receive a reference potential thereon selectively established in response to an applied potential designating signal.
Claim 12
Dependent Claim
125 words
A storage element for storing multi-data of different addresses comprising: a first transistor element having a control electrode coupled to receive a first row select signal, a first conduction terminal coupled to a common node and a second conduction terminal coupled to a first internal data transmission line; and a second transistor element having a control electrode coupled to receive a second row select signal generated independently of said first row select signal, a first conduction terminal coupled to the common node, and a second conduction terminal coupled to a second internal data transmission line; said common node coupled to one of at least three reference potential transmitting lines to receive a reference potential thereon selectively established in response to an applied potential designating signal.
Claim 13
Dependent Claim
140 words
A semiconductor read only memory device comprising: a plurality of word lines and a plurality of bit lines arranged in a plurality of rows and columns; at least three voltage reference lines; a plurality of memory cells arranged in a matrix, each memory cell being able to store multi-data of different addresses and comprising at least one transistor having a control electrode connected to a respective one of said word lines, a first conduction terminal directly connected to a respective one of said bit lines, and a second conduction terminal being connected in one of either the two following manners, i. directly connected to one of said voltage reference lines, and ii. disconnected from all of said voltage reference lines; and means for selectively establishing the voltage level of at least one of said at least three voltage reference lines.
Claim 14
Dependent Claim
140 words
A semiconductor read only memory device comprising: a plurality of word lines and a plurality of bit lines arranged in a plurality of rows and columns; at least three voltage reference lines; a plurality of memory cells arranged in a matrix, each memory cell being able to store multi-data of different addresses and comprising at least one transistor having a control electrode connected to a respective one of said word lines, a first conduction terminal directly connected to a respective one of said bit lines, and a second conduction terminal being connected in one of either the two following manners, i. directly connected to one of said voltage reference lines, and ii. disconnected from all of said voltage reference lines; and means for selectively establishing the voltage level of at least one of said at least three voltage reference lines.
Claim 15
Dependent Claim
39 words
A semiconductor read only memory device as recited in claim 9, wherein each memory cell comprises two transistors, the second conduction terminal of each of said two transistors being connected in common to one of said voltage reference lines.
Claim 16
Dependent Claim
108 words
In a storage element including a transistor element having a first conduction terminal at one, but not both, of either of two states, i. an open state, and ii. a state of receiving a reference potential, said storage element storing multi-data of different addresses, a method of reading data comprising the steps of: selectively establishing a potential at said first conduction terminal according to an externally applied potential designating signal in any access cycle for access to said storage element; and according to an applied address, rendering said transistor element conductive to form a current flow path between said first conduction terminal and an internal data transmission line.
Claim 17
Dependent Claim
108 words
In a storage element including a transistor element having a first conduction terminal at one, but not both, of either of two states, i. an open state, and ii. a state of receiving a reference potential, said storage element storing multi-data of different addresses, a method of reading data comprising the steps of: selectively establishing a potential at said first conduction terminal according to an externally applied potential designating signal in any access cycle for access to said storage element; and according to an applied address, rendering said transistor element conductive to form a current flow path between said first conduction terminal and an internal data transmission line.
Claim 18
Dependent Claim
90 words
In a storage element including a transistor element having a first conduction terminal coupled to receive a reference potential, said storage element storing multi-data of different addresses, a method of reading data comprising the steps of: selectively establishing potential at said first conduction terminal according to an externally applied potential designating signal in any access cycle for access to said storage element; and according to an applied address, rendering said transistor element conductive to form a current flow path between said first conduction terminal and an internal data transmission line.
Claim 19
Dependent Claim
90 words
In a storage element including a transistor element having a first conduction terminal coupled to receive a reference potential, said storage element storing multi-data of different addresses, a method of reading data comprising the steps of: selectively establishing potential at said first conduction terminal according to an externally applied potential designating signal in any access cycle for access to said storage element; and according to an applied address, rendering said transistor element conductive to form a current flow path between said first conduction terminal and an internal data transmission line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |