Non-volatile memory

Claim 2

A non-volatile memory cell of which includes a single MOS transistor, comprising: a semiconductor substrate; source and drain diffusion layers and a channel region between said source and diffusion layers formed on a surface of said semiconductor substrate; a gate electrode disposed over said semiconductor substrate with a gate insulating film interposed between said gate electrode and said channel region; and a programmable insulating film provided in self-alignment between said gate electrode and either one of said source and drain diffusion layers so that said programmable insulating film is selectively broken down by a predetermined voltage applied to said gate electrode to execute programming and electrically conduct between said gate electrode and either one of said source and drain diffusion layers, and a breakdown voltage of said gate insulating film is higher than that of said programmable insulating film and said predetermined voltage; said gate insulating film and said programmable insulating film disposed adjacent to each other under said gate electrode.

Claim 3

A non-volatile memory cell according to claim 1, wherein said gate insulating film comprises an SiO 2 film and said programmable insulating film comprising an Si x N 1-x film (0<X<1) which requires a smaller charge for being broken down than said SiO 2 film.

Claim 4

A non-volatile memory according to claim 1, wherein said programmable insulating film is provided on an upper surface of said gate electrode and on side walls of said gate electrode including either one of said source and drain diffusion layer regions.

Claim 5

A non-volatile memory according to claim 1, wherein said programmable insulating film is provided in self-alignment between said gate electrode and said diffusion layer.

Claim 6

A non-volatile memory cell according to claim 1, wherein either said source or drain diffusion layer is grounded at a side free from the formation of said programmable insulating film at the time of programming.

Claim 7

A non-volatile memory cell of which includes a single MOS transistor, comprising: a semiconductor substrate; source and drain diffusion layers and a channel region between said source and drain diffusion layers formed on a surface of said semiconductor substrate; a gate electrode disposed over said semiconductor substrate with a gate insulating film interposed between said gate electrode and said channel region; and a programmable insulating film provided in self-alignment between said gate electrode and either one of said source and drain diffusion layers and between said gate electrode and a polysilicon spacer in ohmic contact with at least one of said source and drain diffusion layers and on a side wall of said gate electrode so that said programmable insulating film is selectively broken down by a voltage applied to said gate electrode to execute programming and electrically conduct between said gate electrode and either one of said source and drain diffusion layers, and a breakdown voltage of said programmable insulating film is smaller than that of said gate insulating film.

Claim 8

A non-volatile memory cell of which includes a single MOS transistor, comprising: a semiconductor substrate; source and drain diffusion layers and a channel region between said source and drain diffusion layers formed on a surface of said semiconductor substrate; a gate electrode disposed over said semiconductor substrate with a gate insulating film interposed between said gate electrode and said channel region; and a programmable insulating film provided in self-alignment between said gate electrode and either one of said source and drain diffusion layers and between said gate electrode and a polysilicon spacer in ohmic contact with at least one of said source and drain diffusion layers and on a side wall of said gate electrode so that said programmable insulating film is selectively broken down by a voltage applied to said gate electrode to execute programming and electrically conduct between said gate electrode and either one of said source and drain diffusion layers, and a breakdown voltage of said programmable insulating film is smaller than that of said gate insulating film.

Claim 9

A non-volatile memory cell according to claim 6, wherein said gate insulating film comprises an SiO 2 film and said programmable insulating film comprising an Si x N 1-x film (0<X<1) which requires a smaller charge for being broken down than said SiO 2 film.

Claim 10

A non-volatile memory cell according to claim 6, wherein either said source or drain diffusion layer is grounded at a side free from the formation of said programmable insulating film at the time of programming.