Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device

Claim 2

An in-system programmable logic device comprising a common interface for accessing boundary scan testing and in-system programming functions, wherein said common interface distinguishes boundary-scan testing and in-system programming functions using a control signal protocol applied to a set of pins of said common interface.

Claim 3

An in-system programmable logic device as in claim 1, wherein said common interface comprises a first pin for receiving an enable signal, said enable signal having a first state and a second state, said first state enabling in-system programming of said device and said second state enabling a boundary-scan test function of said device.

Claim 4

The in-system programmable logic device of claim 1, wherein said common interface invokes an in-system programming state machine to perform in-system programming functions and a boundary-scan state machine to perform boundary scan testing functions.

Claim 5

An in-system programmable logic device as in claim 1, wherein said common interface comprises a common state machine for performing both in-system programming of said device and boundary-scan testing said device, said state machine executing an instruction set including an instruction for an in-system programming function and an instruction for a boundary-scan testing function.

Claim 6

The in-system programmable logic device of claim 4, wherein said state machine uses an instruction register, said instruction register providing an instruction to perform said in-system programming of said device.

Claim 7

The in-system programmable logic device of claim 5, wherein said state machine further comprises, an address shift register; a data shift register; a generic logic block (GLB) register; and an input/output register; wherein said address shift register, said data shift register, said GLB register and said input/output register receive said instructions from said instruction register.

Claim 8

An in-system programmable logic device comprising a common interface for accessing boundary scan testing and in-system programming functions, wherein said common interface comprises: a first pin for receiving an enable signal, said enable signal having a first state and a second state, said first state enabling in-system programming of said device and said second state enabling a boundary-scan test function of said device, a second pin for receiving a mode input signal for performing in-system programming when said enable signal is in said first state, said second pin receiving a test mode select signal for performing a boundary-scan test function when in said second state; a third pin for receiving a serial data input signal for performing in-system programming when said enable signal is in said first state, said third pin receiving a test data input signal for performing a boundary-scan test function when said enable signal is in said second state; a fourth pin for receiving a shift clock signal for performing in-system programming when said enable signal is in said first state, said fourth pin receiving a test clock signal for performing a boundary-scan test function when said enable signal is in said second state; and a fifth pin for providing a serial data output signal for performing in-system programming when said enable signal is in said first state, said fifth pin providing a test data output signal for performing a boundary-scan function when said enable signal is in said second state.

Claim 9

An in-system programmable logic device comprising a common interface for accessing boundary scan testing and in-system programming functions, wherein said common interface comprises: a first pin for receiving an enable signal, said enable signal having a first state and a second state, said first state enabling in-system programming of said device and said second state enabling a boundary-scan test function of said device, a second pin for receiving a mode input signal for performing in-system programming when said enable signal is in said first state, said second pin receiving a test mode select signal for performing a boundary-scan test function when in said second state; a third pin for receiving a serial data input signal for performing in-system programming when said enable signal is in said first state, said third pin receiving a test data input signal for performing a boundary-scan test function when said enable signal is in said second state; a fourth pin for receiving a shift clock signal for performing in-system programming when said enable signal is in said first state, said fourth pin receiving a test clock signal for performing a boundary-scan test function when said enable signal is in said second state; and a fifth pin for providing a serial data output signal for performing in-system programming when said enable signal is in said first state, said fifth pin providing a test data output signal for performing a boundary-scan function when said enable signal is in said second state.

Claim 12

A method of controlling an in-system programmable logic device as in claim 8, wherein said step of invoking further comprises the steps of: applying an enable signal having a first state and a second state to a first pin of said device; accessing an in-system programming function of said device if said enable signal is in said first state; and accessing a boundary-scan test function of said device if said enable signal is in said second state.

Claim 13

The method of claim 9, further comprising the steps of: utilizing a signal on a second pin as a mode input signal for in-system programming when said enable signal is in said first state and utilizing said signal on said second pin as a test mode select signal for boundary-scan testing when said enable signal is in said second state; utilizing a signal on a third pin as a serial data input signal for in-system programming when said enable signal is in said first state and utilizing said signal on said third pin as a test data input signal for boundary-scan testing when said enable signal is in said second state; utilizing a signal on a fourth pin as a shift clock signal for in-system programming when said enable signal is in said first state and utilizing said signal on said fourth pin as a test clock signal for boundary-scan testing when said enable signal is in said second state; and utilizing a signal on a fifth pin as a serial data output signal for in-system programming when said enable signal is in said first state and utilizing said signal on said fifth pin as a test data output signal for boundary-scan testing when said enable signal is in said second state.

Claim 14

The method of claim 8 wherein said step of providing a common interface comprises the steps of: providing an in-system programming state machine to perform in-system programming functions; and providing a boundary-scan testing state machine to perform boundary-scan testing functions.

Claim 15

A method for controlling an in-system programmable device as in claim 8, wherein said step of providing a common interface comprises the step of providing a state machine for perform both boundary-scan testing and in-system programming, said state machine executing instructions from an instruction set including an instruction for a boundary scan testing function and an instruction for an in-system programming function.

Claim 16

The method of claim 12, further comprising the step of loading an instruction register in accordance with said state machine to provide instructions to perform said in-system programming.

Claim 17

The method of claim 8, wherein said step of providing a common interface provides an interface distinguishing boundary-scan testing and in-system programming functions according to a control signal protocol applied to a set of control pins of said interface.