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US5455796A
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US
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Semiconductor memory device
Assignee: Texas Instruments Inc
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Filing: 1993-08-10
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Granted: 1995-10-03
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Expires: 2013-08-10
Abstract
Abstract A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory/device can be shortened, and the power consumption can be cut. In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.
Inventors
- 👤 Takashi Inui
- 👤 Kiyotaka Okuzawa
- 👤 Yoshihiro Ogata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:52
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
175 words
A semiconductor memory device comprising: memory cells arranged in a matrix configuration; bit lines and word lines connected to said memory cells, for selecting said memory cells; sense amplifiers connected to said bit lines; a decoder circuit connected to said word lines wherein, in a test mode, said decoder circuit selectively drives a plurality of said word lines wherein a multiword control signal, first predecode signals, and second .predecode signals are input to said decoder circuit to select said word lines which are selectively driven, said decoder circuit comprising: first AND gates, each having inputs connected to first predecode signals: OR gates, each having an input connected to an output of one of said first AND gates and each connected to said multiword control signal; second AND gates, each having an input connected to an output of one of said OR gates and each having an input connected to at least one of said second predecode signals, wherein an output of each of said second AND gates is connected to one of said word lines.
Claim 2
Dependent Claim
175 words
A semiconductor memory device comprising: memory cells arranged in a matrix configuration; bit lines and word lines connected to said memory cells, for selecting said memory cells; sense amplifiers connected to said bit lines; a decoder circuit connected to said word lines wherein, in a test mode, said decoder circuit selectively drives a plurality of said word lines wherein a multiword control signal, first predecode signals, and second .predecode signals are input to said decoder circuit to select said word lines which are selectively driven, said decoder circuit comprising: first AND gates, each having inputs connected to first predecode signals: OR gates, each having an input connected to an output of one of said first AND gates and each connected to said multiword control signal; second AND gates, each having an input connected to an output of one of said OR gates and each having an input connected to at least one of said second predecode signals, wherein an output of each of said second AND gates is connected to one of said word lines.
Claim 3
Dependent Claim
33 words
The device of claim 1, wherein said sense amplifiers that are in a driving state, are not reset during the time said plurality of word lines are driven, whereby power consumption is reduced.
Claim 4
Dependent Claim
18 words
The device of claim 1, wherein said device further comprises an element isolating layout of said memory cells.
Claim 5
Dependent Claim
23 words
The device of claim 3, wherein there is a prescribed interval between said selectively driven word lines corresponding to said element isolating layout.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-02 | 1999-04-03 | 1999-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-02 | 2003-04-03 | 2003-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-02 | 2007-04-03 | 2007-10-03 | $7700.00 | Window Closed / Lapsed |