Electrically programmable memory device with improved dual floating gates

Claim 1

An improved erasable programmable read only memory device, having dual sidewall floating gates comprising: a tunnel oxide layer on the surface of a monocrystalline silicon semiconductor substrate having a background impurity of a first conductivity type; spaced field oxide regions on the substrate surface; spaced apart dual floating gates on the substrate surface between the field oxide regions; a first drain region, second drain region and central source regions spaced apart of a second conductivity type at the substrate surface, said first drain region and second drain region spaced apart by the dual floating gates structure and the central source region, the central source region located between the dual floating gates; an insulating layer on the substrate surface, on the tunnel oxide layer over the source region and drain region, and on the dual floating gates; a conductive layer on the second insulating layer thereby acting as the control gate; and electrical contacts and metallurgy lines with appropriate passivation, and connecting the source and drain regions and gate elements to form an erasable programmable memory device.