US5229631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Erase performance improvement via dual floating gate processing
Assignee: Intel Corp
•
Filing: 1992-10-20
•
Granted: 1993-07-20
•
Expires: 2012-10-20
Abstract
Abstract A process for fabricating floating gates for electrically programmable and electrically erasable memory cells of the flash EPROM or EEPROM type. The floating gates are a three layer structure. The first layer of the floating gate is a thin polysilicon layer of approximately 300-500 Å thickness. The second layer is a silicon dioxide layer of approximately 20-30 Å. The third layer is polysilicon of approximately 1000-1500 Å thickness. The third layer is doped by implantation of phosphorous. This dopant is driven through the oxide layer to dope the first, thin polysilicon layer in a separate diffusion step or in subsequent high temperature processing. The grain size of the first, thin polysilicon layer is small and uniform from gate to gate due to the thinness of this layer and its light doping. This reduces variations in threshold voltage from gate to gate due to variable polysilicon grain size and orientation. This in turn results in improved yield and cycling endurance.
Inventors
- 👤 Been-Jon Woo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:32
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
110 words
A floating gate member in a non-volatile memory device, comprising: a first polysilicon layer disposed on a tunnel oxide, said first polysilicon layer forming a first portion of said floating gate member; an insulative layer disposed on said first polysilicon layer, said insulative layer forming a second portion of said floating gate member; and a second polysilicon layer disposed on said insulative layer, said second polysilicon layer forming a third portion of said floating gate member, wherein said second polysilicon layer has a dopant concentration of approximately 1×10 20 ions/cm 3 or less, and wherein said second polysilicon layer is doped to a greater concentration than said first polysilicon layer.
Claim 2
Dependent Claim
110 words
A floating gate member in a non-volatile memory device, comprising: a first polysilicon layer disposed on a tunnel oxide, said first polysilicon layer forming a first portion of said floating gate member; an insulative layer disposed on said first polysilicon layer, said insulative layer forming a second portion of said floating gate member; and a second polysilicon layer disposed on said insulative layer, said second polysilicon layer forming a third portion of said floating gate member, wherein said second polysilicon layer has a dopant concentration of approximately 1×10 20 ions/cm 3 or less, and wherein said second polysilicon layer is doped to a greater concentration than said first polysilicon layer.
Claim 3
Dependent Claim
36 words
The floating gate member as defined in claim 1 wherein said first polysilicon layer is in the range of 200-700 Å and the thickness of said second polysilicon layer is in the range of 800-2000 Å.
Claim 4
Dependent Claim
23 words
The floating gate member as defined in claim 1 wherein the thickness of said insulative layer is in the range of 15-50 Å.
Claim 5
Dependent Claim
23 words
The floating gate member as defined in claim 2 wherein the thickness of said insulative layer is in the range of 15-50 Å.
Claim 6
Dependent Claim
20 words
The floating gate member as defined in claim 1, 2, 3 or 4 wherein said insulative layer comprises silicon dioxide.
Claim 7
Dependent Claim
122 words
An array of floating gate memory devices, each of said devices comprising a floating gate member, said floating gate member comprising: a first polysilicon layer disposed on a tunnel oxide layer, said first polysilicon layer forming a first portion of said floating gate member; an insulative layer disposed on said first polysilicon layer, said insulative layer forming a second portion of said floating gate member; and a second polysilicon layer disposed on said insulative layer, said second polysilicon layer forming a third portion of said floating gate member, wherein said second polysilicon layer has a dopant concentration of approximately 1×10 20 ions/cm 3 or less, and wherein said second polysilicon layer is doped to a greater concentration than said first polysilicon layer.
Claim 8
Dependent Claim
122 words
An array of floating gate memory devices, each of said devices comprising a floating gate member, said floating gate member comprising: a first polysilicon layer disposed on a tunnel oxide layer, said first polysilicon layer forming a first portion of said floating gate member; an insulative layer disposed on said first polysilicon layer, said insulative layer forming a second portion of said floating gate member; and a second polysilicon layer disposed on said insulative layer, said second polysilicon layer forming a third portion of said floating gate member, wherein said second polysilicon layer has a dopant concentration of approximately 1×10 20 ions/cm 3 or less, and wherein said second polysilicon layer is doped to a greater concentration than said first polysilicon layer.
Claim 9
Dependent Claim
34 words
The array as defined in claim 6 wherein said first polysilicon layer is in the range of 200-700 Å and the thickness of said second polysilicon layer is in the range of 800-2000 Å.
Claim 10
Dependent Claim
21 words
The array as defined in claim 6 wherein the thickness of said insulative layer is in the range of 15-50 Å.
Claim 11
Dependent Claim
21 words
The array as defined in claim 7 wherein the thickness of said insulative layer is in the range of 15-50 Å.
Claim 12
Dependent Claim
18 words
The array as defined in claim 6, 7, 8 or 9 wherein said insulative layer comprises silicon dioxide.
Claim 13
Dependent Claim
24 words
The array as defined in claim 6 wherein the grain size of said first polysilicon layer is uniform in all of said floating gates.
Claim 14
Dependent Claim
24 words
The array as defined in claim 7 wherein the grain size of said first polysilicon layer is uniform in all of said floating gates.
Claim 15
Dependent Claim
24 words
The array as defined in claim 8 wherein the grain size of said first polysilicon layer is uniform in all of said floating gates.
Claim 16
Dependent Claim
24 words
The array as defined in claim 9 wherein the grain size of said first polysilicon layer is uniform in all of said floating gates.
Claim 17
Dependent Claim
24 words
The array as defined in claim 10 wherein the grain size of said first polysilicon layer is uniform in all of said floating gates.
Claim 18
Dependent Claim
24 words
The array as defined in claim 6 wherein the grain size of said first polysilicon layer is uniform in all of said floating gates.
References Cited (Backward Citations)
JPS5389686A
Cited
US4926222A
Cited
JPS5766675A
Cited
JPS5787176A
Cited
US4365405A
Cited
US4517732A
Cited
JPS6010679A
Cited
US4701776A
Cited
US4597159A
Cited
US4719184A
Cited
US4768080A
Cited
JPS61181168A
Cited
JPS61255071A
Cited
US4742491A
Cited
US5008722A
Cited
US4766473A
Cited
US4812885A
Cited
JPH01132169A
Cited
US4966572A
Cited
US4957877A
Cited
US5028979A
Cited
US5063423A
Cited
US4994403A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-19 | 1997-01-18 | 1997-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-19 | 2001-01-18 | 2001-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-19 | 2005-01-18 | 2005-07-20 | $7700.00 | Window Closed / Lapsed |