US5532971A
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US
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Nonvolatile semiconductor memory having enhanced speed for erasing and programming
Assignee: Renesas Electronics Corp
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Filing: 1994-12-13
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Granted: 1996-07-02
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Expires: 2014-12-13
Abstract
Abstract An arrangement is provided to enhance the speed in the operation of erasing and programming of a nonvolatile semiconductor memory that is driven by a single supply voltage and to reduce the number of transistors making up the subword decoder circuit thereby minimizing the size of the device. For this purpose, in the subword decoder circuits WDi1-WDij that drive the word lines Wi1-Wij, the block selection address lines Bip and Bin generated from the first address line group are used as supply voltages for the inverter circuit that controls the voltage of the word line, and the gate selection address line Gj generated from the second address line group is used a gate input line.
Inventors
- 👤 Toshihiro Tanaka
- 👤 Masataka Kato
- 👤 Keiichi Yoshida
- 👤 Hitoshi Kume
- 👤 Yoshinobu Nakagome
- 👤 Katsutaka Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:13
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/08; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/10; G11C16/12; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
120 words
A nonvolatile semiconductor memory comprising: an electrically erasable and programmable nonvolatile memory cell having a control gate, a drain and a source; a word line connected to the control gate of the nonvolatile memory cell; a data line connected to the drain of the nonvolatile memory cell; and a word line drive circuit to drive the word line; wherein the word line drive circuit is an inverter circuit consisting of an n-channel transistor and a p-channel transistor, and the n- and p-channel transistors each have their source line supplied with a block selection address line generated from a first address line group and their gate line supplied with a gate selection address line generated from a second address line group.
Claim 2
Dependent Claim
120 words
A nonvolatile semiconductor memory comprising: an electrically erasable and programmable nonvolatile memory cell having a control gate, a drain and a source; a word line connected to the control gate of the nonvolatile memory cell; a data line connected to the drain of the nonvolatile memory cell; and a word line drive circuit to drive the word line; wherein the word line drive circuit is an inverter circuit consisting of an n-channel transistor and a p-channel transistor, and the n- and p-channel transistors each have their source line supplied with a block selection address line generated from a first address line group and their gate line supplied with a gate selection address line generated from a second address line group.
Claim 3
Dependent Claim
46 words
A nonvolatile semiconductor memory according to claim 1, wherein during a reprogramming operation of lowering a threshold voltage of the nonvolatile memory cell, a negative voltage is applied to the word line through a source-drain path of the n-channel transistor in the word line drive circuit.
Claim 4
Dependent Claim
52 words
A nonvolatile semiconductor memory according to claim 2, wherein during the reprogramming operation, the application to the word line of the negative voltage is stopped temporarily, a positive voltage lower than the supply voltage is applied to the word line, and then the negative voltage is applied to the word line again.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-02 | 2000-01-01 | 2000-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-02 | 2004-01-01 | 2004-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-02 | 2008-01-01 | 2008-07-02 | $7700.00 | Window Closed / Lapsed |