Minimum-delay jitter smoothing device and method for packet video communications

Claim 3

The device of claim 1 wherein the predetermined scheme includes inserting the stuffing bits into the bitstream when one of: (A) a predetermined hypothetical decoder buffer condition is violated; and (B) the video information buffer is empty.

Claim 4

The device of claim 1 wherein the fullness, B n , of the hypothetical decoder buffer (HDB) at time t n is determined according to B n =B n-1 +Rn -1 ,n, where B n-1 is the buffer fullness at time t n-1 , and R n-1 ,n is the number of video information bits transmitted during frame interval n-1 from time t n-1 to t n .

Claim 5

The device of claim 2 wherein the predetermined hypothetical decoder buffer condition is violated when E n <B n-1 +R n-1 ,n+1 -S, where E n is the number of information bits removed from the HDB for frame n, B n-1 is the HDB fullness at time t n-1 , R n-1 ,n+1 is the number of information bits transmitted from time t n-1 to t n+1 , and S is the size of the HDB.

Claim 6

The device of claim 4 wherein the predetermined hypothetical buffer condition is checked once every frame interval, and when the predetermined hypothetical buffer condition is violated, the stuffing bits are output to the bitstream generator before sending any video information bits from the video information buffer.

Claim 7

The device of claim 5 wherein the minimum number of stuffing bits S n is determined by S n =B n-1 +R n-1 ,n+1 -S-E n .

Claim 8

The device of claim 1 wherein the video decoder is an H.261 decoder.

Claim 9

The device of claim 7 wherein the bits stuffing is performed utilizing one of: (A) macroblock address stuffing; and (B) error correction framing.

Claim 10

The device of claim 1 wherein a predetermined rate for reading video information bits from the video information buffer is selectable.

Claim 11

The device of claim 1 wherein the decoder buffer verifier includes: (A) a frame bit counter, operably coupled to the video information buffer, for counting a number of bits for each video frame E n , (B) a HDB fullness counter, operably coupled to the video information buffer, for counting a HDB fullness B n , (C) a buffer condition verifier, operably coupled to the frame bit counter and to the HDB fullness counter, for verifying whether the number of the bits for a preselected frame removed from the HDB satisfies a predetermined hypothetical decoder buffer condition, and, where the predetermined hypothetical decoder buffer condition is violated, for providing to the bitstream generator a number equal to the number of stuffing bits S n .

Claim 12

The device of claim 1 wherein the bitstream generator includes: (A) a stuffing bits generator, operably coupled to the video information buffer, to the buffer condition verifier, and to a stuffing bit buffer, for generating stuffing bits in accordance with the predetermined scheme, (B) the stuffing bits buffer, operably coupled to the stuffing bits generator, for storing the generated stuffing bits and for providing the stuffing bits to an output switch in accordance with occurrence of one of selected predetermined occurrences, (C) the output switch, operably coupled to the video information buffer and to the stuffing bits buffer, for receiving one of: (C1) input from the stuffing bits buffer upon occurrence of one of the selected predetermined occurrences, and (C2) input from the video information buffer upon nonoccurrence of one of the selected predetermined occurrences.

Claim 15

The method of claim 12 wherein the predetermined scheme includes inserting the stuffing bits into the bitstream when one of: (A) a predetermined hypothetical buffer condition is violated; and (B) the video information buffer is empty.

Claim 16

The method of claim 12 wherein the fullness Bn of a hypothetical decoder buffer (HDB) at time tn, which is just before frame n is removed from the hypothetical decoder, is determined according to Bn=Bn-1+Rn-1,n, where Bn-1 is the buffer fullness just after frame n-1 is removed from the hypothetical decoder, and Rn-1,n is the number of video information bits transmitted during frame interval n-1 from time tn-1 to tn.

Claim 17

The method of claim 13 wherein the predetermined hypothetical decoder buffer condition is violated when E n <B n-1 +R n-1 ,n+1 -S, where E n is the number of information bits removed from the hypothetical decoder buffer for frame n, B n-1 is the hypothetical decoder buffer fullness at time tn-1, R n-1 ,n+1 is the number of information bits transmitted from time tn-1 to tn+1, and S is the size of the hypothetical decoder buffer.

Claim 18

The method of claim 15 wherein the predetermined hypothetical buffer condition is checked at every frame interval, and when the predetermined hypothetical buffer condition is violated, the stuffing bits are output to the bitstream generator before sending any video information bits from the video information buffer.

Claim 19

The method of claim 16 wherein the minimum number of stuffing bits S n is determined by S n =B n-1 +R n-1 ,n+1 -S-E n .

Claim 20

The method of claim 12 wherein the external decoder is an H.261 decoder.

Claim 21

The method of claim 18 wherein the bits stuffing is performed utilizing one of: (A) macroblock address stuffing; and (B) error correction framing.

Claim 22

The method of claim 12 wherein a predetermined rate for reading video information bits from the video information buffer is selectable.

Claim 23

The method of claim 12 wherein the step of monitoring a fullness of a hypothetical decoder buffer by a decoder buffer verifier (DBV)includes: (A) utilizing a frame bit counter for counting a number of bits for each frame En transmitted from the video information buffer, (B) utilizing a decoder buffer fullness counter for counting a decoder buffer fullness Bn, (C) utilizing a buffer condition verifier for verifying whether the number of bits for a preselected frame removed from the HDB satisfies a predetermined hypothetical decoder buffer condition, and, when the predetermined hypothetical decoder buffer condition is violated, providing to the bitstream generator a number equal to the number of stuffing bits Sn.

Claim 24

The method of claim 12 wherein the step of reading, by a bitstream generator, video information bits from the video information buffer at a predetermined rate and inserting, by the bitstream generator, a number of stuffing bits into the video information bitstream wherein the number of stuffing bits is determined according to a predetermined scheme to provide substantially minimized delay jitter smoothing includes: (A) utilizing a stuffing bits generator for generating stuffing bits in accordance with the predetermined scheme, (B) utilizing a stuffing bits buffer for storing the generated stuffing bits and providing the stuffing bits to an output switch in accordance with occurrence of one of selected predetermined occurrences, (C) utilizing the output switch for receiving one of: (C1) input from the stuffing bits buffer upon occurrence of one of the selected predetermined occurrences, and (C2) input from the video information buffer upon nonoccurrence of one of the selected predetermined occurrences.

Claim 25

The method of claim 22 wherein the selected predetermined occurrences include: (A) where a frame is removed from the HDB, a nonzero Sn inputted from the buffer condition verifier, the stuffing bits generator generates Sn stuffing bits in compliance with a preselected decoder bitstream syntax, and where a number of the generated stuffing bits S n is different from Sn, S n is selected to be a smallest number that is no less than Sn in order to reduce incurred delay at a decoder, and (B) where both the video information buffer and the stuffing bits buffer are empty, the stuffing bits generator generates a minimum number of stuffing bits that is in compliance with the preselected decoder bitstream syntax to ensure that channel will not be idle.

Claim 26

A hypothetical buffer-based jitter smoothing device for minimizing smoothing delay in a packet video communication system, the device comprising: A) a video depacketizer, operably coupled to receive and depacketize digital video packets of a received digital video packet stream into video information bits, B) an information buffer, operably coupled to the depacketizing means, for storing the video information bits, C) hypothetical buffer-based smoothing means, operably coupled to the information buffer, for utilizing a hypothetical buffer to generate and transmit a continuous stuffed video information bitstream at a predetermined rate and minimize buffering jitter.

Claim 27

A hypothetical buffer-based jitter smoothing device for minimizing smoothing delay in a packet video communication system, the device comprising: A) a video depacketizer, operably coupled to receive and depacketize digital video packets of a received digital video packet stream into video information bits, B) an information buffer, operably coupled to the depacketizing means, for storing the video information bits, C) hypothetical buffer-based smoothing means, operably coupled to the information buffer, for utilizing a hypothetical buffer to generate and transmit a continuous stuffed video information bitstream at a predetermined rate and minimize buffering jitter.

Claim 28

The hypothetical buffer-based jitter smoothing device of claim 24 wherein a number of stuffing bits inserted into the video information bitstream is determined according to a predetermined scheme.

Claim 29

The hypothetical buffer-based jitter smoothing device of claim 24 wherein the hypothetical buffer-based smoothing means determines a number of stuffing bits to be transmitted for a video frame and monitors a fullness of the hypothetical buffer.

Claim 30

The hypothetical buffer-based jitter smoothing device of claim 25 wherein the predetermined scheme includes inserting the stuffing bits into the bitstream, i.e., bits stuffing, when one of: (A) a predetermined hypothetical buffer condition is violated; and (B) the video information buffer is empty.

Claim 31

The hypothetical buffer-based jitter smoothing device of claim 26 wherein the fullness, B n , of the hypothetical buffer at time t n is determined according to B n =B n-1 +Rn 31 1 ,n, where B n-1 is the buffer fullness at time t n-1 , and R n-1 ,n is the number of video information bits transmitted during frame interval n-1 from time t n-1 to t n .

Claim 32

The hypothetical buffer-based jitter smoothing device of claim 27 wherein the predetermined hypothetical buffer condition is violated when E n <B n-1 +R n-1 ,n+1 -S, where E n is the number of information bits removed from the hypothetical buffer for frame n, B n-1 is the fullness of said buffer at time t n-1 , R n-1 ,n+1 is the number of information bits transmitted from time t n-1 to t n+1 , and S is the size of the hypothetical buffer.

Claim 33

The hypothetical buffer-based jitter smoothing device of claim 27 wherein the predetermined hypothetical buffer condition is checked once every frame interval, and when the predetermined hypothetical buffer condition is violated, the stuffing bits are inserted into the video information bitstream before sending any video information bits from the video information buffer.

Claim 34

The hypothetical buffer-based jitter smoothing device of claim 30 wherein the minimum number of stuffing bits S n is determined by S n =B n-1 +R n-1 ,n+1 -S-E n .

Claim 35

The hypothetical buffer-based jitter smoothing device of claim 24 wherein the continuous stuffed video information bitstream output from the jitter smoothing device is transmitted to an H.261 decoder.

Claim 36

The hypothetical buffer-based jitter smoothing device of claim 32 wherein the bits stuffing is performed utilizing one of: (A) macroblock address stuffing; and (B) error correction framing.

Claim 37

The hypothetical buffer-based jitter smoothing device of claim 26 wherein determining the number of stuffing bits to be transmitted for the video frame is performed at a predetermined selectable rate.

Claim 38

The hypothetical buffer-based jitter smoothing device of claim 24 wherein the hypothetical buffer-based smoothing means includes: (A) a frame bit counter, operably coupled to the video information buffer, for counting a number of bits for each video frame E n , (B) a hypothetical buffer fullness counter, operably coupled to the video information buffer, for counting a hypothetical buffer fullness B n , (C) a buffer condition verifier, operably coupled to the frame bit counter and to the hypothetical buffer fullness counter, for verifying whether the number of the bits for a preselected frame removed from the hypothetical buffer satisfies a predetermined hypothetical buffer condition, and, where the predetermined hypothetical buffer condition is violated, for providing to the bitstream generator a number equal to the number of stuffing bits S n , (D) a stuffing bits generator, operably coupled to the video information buffer, to the buffer condition verifier, and to a stuffing bit buffer, for generating stuffing bits in accordance with the predetermined scheme, (E) the stuffing bits buffer, operably coupled to the stuffing bits generator, for storing the generated stuffing bits and for providing the stuffing bits to an output switch in accordance with occurrence of one of selected predetermined occurrences, and (F) the output switch, operably coupled to the video information buffer and to the stuffing bits buffer, for receiving one of: (F1) input from the stuffing bits buffer upon occurrence of one of the selected predetermined occurrences, and (F2) input from the video information buffer upon nonoccurrence of one of the selected predetermined occurrences.