US5553018A
Expired / Lapsed
US
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Nonvolatile memory cell formed using self aligned source implant
Assignee: Cypress Semiconductor Corp
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Filing: 1995-06-07
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Granted: 1996-09-03
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Expires: 2015-06-07
Abstract
Abstract A memory device, such as a flash EEPROM, employs a high energy implantation to form common source line, avoiding the necessity of self-aligned source etch processes. The use of the high energy implantation, and avoiding the etching process, provides for greater cell uniformity, and better VT distribution.
Inventors
- 👤 Hsingya A. Wang
- 👤 James J. Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:44
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
89 words
A high density floating gate memory cell array formed in a semiconductor substrate, where each cell comprises source, channel and drain semiconductor regions in the substrate, the array comprising: respective columns of cells; respective continuous strips of field oxide, interposed between adjacent columns of cells; respective stacked-gate-word-line structures disposed extending over the field oxide strips, and overlying the channel regions of each cell in a row of cells; and implanted interconnection regions, extending under the field oxide strips, electrically connecting the source regions of corresponding cells in adjacent columns.
Claim 2
Dependent Claim
89 words
A high density floating gate memory cell array formed in a semiconductor substrate, where each cell comprises source, channel and drain semiconductor regions in the substrate, the array comprising: respective columns of cells; respective continuous strips of field oxide, interposed between adjacent columns of cells; respective stacked-gate-word-line structures disposed extending over the field oxide strips, and overlying the channel regions of each cell in a row of cells; and implanted interconnection regions, extending under the field oxide strips, electrically connecting the source regions of corresponding cells in adjacent columns.
Claim 3
Dependent Claim
19 words
The memory cell array of claim 1, where the resistance of the interconnection regions is less than two square.
Claim 4
Dependent Claim
19 words
The memory cell array of claim 1, where the resistance of the interconnection regions is less than one square.
Claim 5
Dependent Claim
18 words
The memory cell array of claim 1, where the resistance of the interconnection regions is approximately 0.75 square.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-03 | 2000-03-04 | 2000-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-03 | 2004-03-04 | 2004-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-03 | 2008-03-04 | 2008-09-03 | $7700.00 | Window Closed / Lapsed |