High-performance integrated bit-mapped graphics controller

Claim 2

A computer bit-mapped video controller on a semiconductor die comprising: a video controller functional block on the semiconductor die; a video frame buffer memory on the semiconductor die, said video frame buffer memory being organized in an "n"-bit wide format, wherein "n" is at least 128 bits, said video frame buffer memory being closely coupled to said video controller functional block by an "n" bit wide parallel bus, whereby the refresh rate of the video frame buffer memory is reduced; an interface on the semiconductor die for interfacing between the video controller functional block and a host computer; first means on the semiconductor die for retrieving pixel data from the video frame buffer memory in the "n"-bit wide format over the "n" bit wide parallel bus, wherein "n" is at least 128 bits, and providing said pixel data in a serial video format; and second means on the semiconductor die for exchanging pixel data between the video controller functional block and the video frame buffer memory in the "n"-bit wide format over the "n" bit wide parallel bus, wherein "n" is at least 128 bits.

Claim 3

The computer bit-mapped video controller according to claim 1, wherein: the video frame buffer has a width of at least 256 bits.

Claim 4

The computer bit-mapped video controller according to claim 1, wherein: the video frame buffer has a width of at least 512 bits.

Claim 5

The computer bit-mapped video controller according to claim 1, wherein: the video frame buffer has a width of at least 768 bits.

Claim 6

The computer bit-mapped video controller according to claim 1, wherein: the video frame buffer has a width of at least 1024 bits.

Claim 7

The computer bit-mapped video controller according to claim 1, wherein: the second means includes a cache memory.

Claim 8

The computer bit-mapped video controller according to claim 1, wherein: the second means includes a first-in first-out (FIFO) buffer.

Claim 9

A computer bit-mapped video controller on a semiconductor die comprising: a video controller functional block on the semiconductor die; a one megabyte video frame buffer memory on the semiconductor die, said video frame buffer memory being organized as a 256 bit wide by 32,768 bit deep video memory, said video frame buffer memory being closely coupled to said video controller functional block, whereby the refresh rate of the video frame buffer memory is reduced; an interface on the semiconductor die for interfacing between the video controller functional block and a host computer; first means on the semiconductor die for retrieving 256 bit wide pixel data from the video frame buffer memory by accessing said pixel data in said video frame buffer memory and providing said pixel data in a serial video format; second means for providing one or more video synchronizing signals; a cache memory on the semiconductor die, logically positioned between the video controller functional block and the video frame buffer memory, and providing a 256 bit wide buffer for pixel data accesses therebetween: and third means on the semiconductor die for interleaving video frame buffer memory accesses such that pixel data accesses from the video controller functional block via the cache memory are permitted only between pixel data accesses by the first means.

Claim 10

A computer bit-mapped video controller on a semiconductor die comprising: a video controller functional block on the semiconductor die; a one megabyte video frame buffer memory on the semiconductor die, said video frame buffer memory being organized as a 256 bit wide by 32,768 bit deep video memory, said video frame buffer memory being closely coupled to said video controller functional block, whereby the refresh rate of the video frame buffer memory is reduced; an interface on the semiconductor die for interfacing between the video controller functional block and a host computer; first means on the semiconductor die for retrieving 256 bit wide pixel data from the video frame buffer memory by accessing said pixel data in said video frame buffer memory and providing said pixel data in a serial video format; second means for providing one or more video synchronizing signals; a cache memory on the semiconductor die, logically positioned between the video controller functional block and the video frame buffer memory, and providing a 256 bit wide buffer for pixel data accesses therebetween: and third means on the semiconductor die for interleaving video frame buffer memory accesses such that pixel data accesses from the video controller functional block via the cache memory are permitted only between pixel data accesses by the first means.

Claim 11

A bit mapped video controller on a semiconductor die for use with a computer system, said video controller comprising: a semiconductor die, said semiconductor die containing; a video memory having at least one megabyte of digital video data storage capacity and arranged in an "n"-bit wide format, wherein "n" is selected from the group of at least 128, 256, 512, 768 and 1024 bits, whereby the refresh rate of the video memory is reduced: a video shift register closely coupled to said video memory for receiving stored digital video data in "n"-bit wide format over an "n"-bit wide parallel bus, said video shift register adapted to output the received stored digital video data in serial video format; an interface adapted for connection to the computer system data address and control buses, said interface closely coupled over the "n"-bit wide parallel bus in "n"-bit wide format to said video memory, said interface transferring digital video data received from the computer system to said video memory; and a logic controller for controlling said interface, video memory and video shift register and the digital video data therebetween.

Claim 12

A bit mapped video controller on a semiconductor die for use with a computer system, said video controller comprising: a semiconductor die, said semiconductor die containing; a video memory having at least one megabyte of digital video data storage capacity and arranged in an "n"-bit wide format, wherein "n" is selected from the group of at least 128, 256, 512, 768 and 1024 bits, whereby the refresh rate of the video memory is reduced: a video shift register closely coupled to said video memory for receiving stored digital video data in "n"-bit wide format over an "n"-bit wide parallel bus, said video shift register adapted to output the received stored digital video data in serial video format; an interface adapted for connection to the computer system data address and control buses, said interface closely coupled over the "n"-bit wide parallel bus in "n"-bit wide format to said video memory, said interface transferring digital video data received from the computer system to said video memory; and a logic controller for controlling said interface, video memory and video shift register and the digital video data therebetween.

Claim 13

The controller of claim 9 further comprising on the semiconductor die a first-in-first-out buffer between said interface and said video memory.

Claim 14

The controller of claim 9, further comprising on the semiconductor die a cache memory between said interface and said video memory.