Patent US3247441A successfully refreshed from Google Patents.
Patent US5587600A successfully refreshed from Google Patents.
US5587600A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Series MOS ROM with tapered oxide side walls
Assignee: United Microelectronics Corp
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Filing: 1996-04-23
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Granted: 1996-12-24
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Expires: 2016-04-23
Abstract
Abstract A read-only-memory having a plurality of very narrow, closely spaced gate electrodes spanning the distance between source and drain regions. The gate electrodes consist of first and second alternating polycrystalline silicon lines having vertical sidewalls. The first lines have tapered sidewall spacers. The second lines are entirely contained between the first lines without overlap of the first lines.
Inventors
- 👤 Ming T. Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:31
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B20/00; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
124 words
An improved read-only-memory device having spaced source and drain regions in a semiconductor substrate, a plurality of very narrow, closely spaced, gate electrodes spanning the distance between the source and drain regions, and an overlying gate oxide layer, the improvement comprised of: electrodes comprising first and second alternating polycrystalline silicon lines on said gate oxide layer, said first lines having sidewalls, and being spaced from each other by approximately the width of each first line; and tapered sidewall spacer elements of insulating material along said sidewalls of each of said first lines, so that said first and second lines are separated by tapered sidewall spacer elements and said first and second lines are more closely spaced near an upper surface of said first lines.
Claim 2
Dependent Claim
124 words
An improved read-only-memory device having spaced source and drain regions in a semiconductor substrate, a plurality of very narrow, closely spaced, gate electrodes spanning the distance between the source and drain regions, and an overlying gate oxide layer, the improvement comprised of: electrodes comprising first and second alternating polycrystalline silicon lines on said gate oxide layer, said first lines having sidewalls, and being spaced from each other by approximately the width of each first line; and tapered sidewall spacer elements of insulating material along said sidewalls of each of said first lines, so that said first and second lines are separated by tapered sidewall spacer elements and said first and second lines are more closely spaced near an upper surface of said first lines.
Claim 3
Dependent Claim
22 words
The memory device of claim 1 which further includes a layer of dielectric material over said first and second polycrystalline silicon lines.
Claim 4
Dependent Claim
25 words
The memory device of claim 1 wherein the thickness of said first and second polycrystalline lines is in the range of 1000 to 6000 angstroms.
Claim 5
Dependent Claim
25 words
The memory device of claim 3 wherein the thickness of said first and second polycrystalline lines is in the range of 2000 to 4000 angstroms.
Claim 6
Dependent Claim
27 words
The memory device of claim 1 wherein said semiconductor substrate has a background P type dopant, and said source and drain regions have an N type dopant.
Claim 7
Dependent Claim
19 words
The memory device of claim 1 wherein there are code implant regions in said substrate beneath selected gate electrodes.
Claim 8
Dependent Claim
22 words
The memory device of claim 1 wherein said gate oxide layer has a thickness in the range of 100 to 300 angstroms.
Claim 9
Dependent Claim
53 words
The memory device of claim 1 wherein code implantations are formed beneath both said first and said second polycrystalline lines, with code implantations beneath said first polycrystalline lines aligned with bases of said first polycrystalline lines and with code implantations beneath said second polycrystalline lines aligned with bases of said second polycrystalline lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-24 | 2000-06-24 | 2000-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-24 | 2004-06-24 | 2004-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-24 | 2008-06-24 | 2008-12-24 | $7700.00 | Window Closed / Lapsed |