High density multistate SRAM and cell

Claim 2

A high density multistate SRAM cell comprising: N negative differential resistance diodes connected in series and connected to a load, the negative differential resistance diodes and the load defining a memory node therebetween having N+1 stable states; a write device having a control terminal, an input terminal adapted to receive N+1 different amplitudes of voltage thereon, and an output terminal connected to the memory node; an amplifier having an input terminal connected to the memory node and an output terminal; and a read switch having an input terminal connected to the output terminal of the amplifier and an output terminal.

Claim 3

A high density multistate SRAM cell as claimed in claim 1 wherein the N negative differential resistance diodes include one of resonant tunneling diodes or Esaki diodes.

Claim 4

A high density multistate SRAM cell as claimed in claim 1 where, in the N negative differential resistance diodes, N is defined as a whole number greater than 1.

Claim 5

A high density multistate SRAM cell as claimed in claim 1 wherein the load is one of an active or passive device.

Claim 6

A high density multistate SRAM cell as claimed in claim 4 wherein the load is one of a transistor or a resistor.

Claim 7

A high density multistate SRAM cell as claimed in claim 1 wherein the write device includes a write transistor having a source, drain, and gate and further having the source connected to the memory node, the drain connected to receive N+1 different amplitudes of voltage thereon, and the gate forming the control terminal and connected to receive a write signal thereon.

Claim 8

A high density multistate SRAM cell as claimed in claim 1 wherein the amplifier includes a transistor having a gate which serves as the input terminal and is connected to the memory node and a drain forming the output terminal.

Claim 9

A high density multistate SRAM cell as claimed in claim 1 wherein the read switch includes a transistor having source, drain, and gate terminals, the source terminal forming the input terminal and connected to the output terminal of the amplifier, the drain terminal forming the output terminal of the read switch and an output terminal of the SRAM, and the gate forming a control terminal and connected to receive a read signal thereon.

Claim 10

A high density multistate SRAM cell comprising: N negative differential resistance diodes connected in series and connected to a load, the negative differential resistance diodes and the load defining a memory node therebetween having N+1 stable states, N being defined as a whole number greater than 1; a write transistor having a control terminal adapted to receive a write signal thereon, an input terminal adapted to receive N+1 different amplitudes of voltage thereon, and an output terminal connected to the memory node; a transistor amplifier having a gate terminal connected to the memory node and an output terminal; and a read transistor having an input terminal connected to the output terminal of the transistor amplifier, a gate adapted to receive a read signal thereon, and an output terminal.

Claim 11

A high density multistate SRAM cell comprising: N negative differential resistance diodes connected in series and connected to a load, the negative differential resistance diodes and the load defining a memory node therebetween having N+1 stable states, N being defined as a whole number greater than 1; a write transistor having a control terminal adapted to receive a write signal thereon, an input terminal adapted to receive N+1 different amplitudes of voltage thereon, and an output terminal connected to the memory node; a transistor amplifier having a gate terminal connected to the memory node and an output terminal; and a read transistor having an input terminal connected to the output terminal of the transistor amplifier, a gate adapted to receive a read signal thereon, and an output terminal.

Claim 12

A high density multistate SRAM comprising: a plurality of individual cells organized in a matrix of rows and columns, each individual cell including N negative differential resistance diodes connected in series and connected to a load, the negative differential resistance diodes and the load defining a memory node therebetween having N+1 stable states, a write device having a control terminal forming a cell write terminal, an input terminal adapted to receive N+1 different amplitudes of voltage thereon and forming a state terminal for the cell, and an output terminal connected to the memory node, an amplifier having an input terminal connected to the memory node and an output terminal, and a read switch having an input terminal connected to the output terminal of the amplifier, an output terminal forming a cell output terminal, and a control terminal forming a cell read terminal; each individual column of the matrix including a state line connected to have N+1 different amplitudes of voltage applied thereto and an output line, the state line of each individual column being connected to the state terminal of each cell in the individual column and the output line of each individual column being connected to the cell output terminal of each cell in the individual column; each individual row of the matrix including a write line connected to the cell write terminal for each cell in the individual row, and a cell read line connected to the cell read terminal of each cell in the individual row; and N+1 sense amplifiers associated with each individual column, each sense amplifier having an input terminal connected to the output line of the associated individual column and an output terminal.

Claim 13

A high density multistate SRAM comprising: a plurality of individual cells organized in a matrix of rows and columns, each individual cell including N negative differential resistance diodes connected in series and connected to a load, the negative differential resistance diodes and the load defining a memory node therebetween having N+1 stable states, a write device having a control terminal forming a cell write terminal, an input terminal adapted to receive N+1 different amplitudes of voltage thereon and forming a state terminal for the cell, and an output terminal connected to the memory node, an amplifier having an input terminal connected to the memory node and an output terminal, and a read switch having an input terminal connected to the output terminal of the amplifier, an output terminal forming a cell output terminal, and a control terminal forming a cell read terminal; each individual column of the matrix including a state line connected to have N+1 different amplitudes of voltage applied thereto and an output line, the state line of each individual column being connected to the state terminal of each cell in the individual column and the output line of each individual column being connected to the cell output terminal of each cell in the individual column; each individual row of the matrix including a write line connected to the cell write terminal for each cell in the individual row, and a cell read line connected to the cell read terminal of each cell in the individual row; and N+1 sense amplifiers associated with each individual column, each sense amplifier having an input terminal connected to the output line of the associated individual column and an output terminal.

Claim 14

A high density multistate SRAM as claimed in claim 10 wherein each of the N+1 sense amplifiers includes a differential amplifier with differential inputs, one differential input being connected to the output line of the associated individual column and another differential input having a reference voltage applied thereto, each of the N+1 sense amplifiers associated with an individual column having a different one of N+1 different amplitudes of reference voltage applied thereto.

Claim 15

A high density multistate SRAM as claimed in claim 10 wherein the N negative differential resistance diodes include one of resonant tunneling diodes or Esaki diodes.

Claim 16

A high density multistate SRAM as claimed in claim 10 where, in the N negative differential resistance diodes, N is defined as a whole number greater than 1.

Claim 17

A high density multistate SRAM as claimed in claim 10 wherein the load is one of an active or passive device.

Claim 18

A high density multistate SRAM as claimed in claim 14 wherein the load is one of a transistor or a resistor.

Claim 19

A high density multistate SRAM as claimed in claim 10 wherein the write device includes a write transistor having a source, drain, and gate and further having the source connected to the memory node, the drain connected to receive N+1 different amplitudes of voltage thereon, and the gate forming the control terminal and connected to receive a write signal thereon.

Claim 20

A high density multistate SRAM as claimed in claim 10 wherein the amplifier includes a transistor having a gate which serves as the input terminal and is connected to the memory node and a drain forming the output terminal.

Claim 21

A high density multistate SRAM as claimed in claim 10 wherein the read switch includes a transistor having source, drain, and gate terminals, the source terminal forming the input terminal and connected to the output terminal of the amplifier, the drain terminal forming the output terminal of the read switch and an output terminal of the SRAM, and the gate forming a control terminal and connected to receive a read signal thereon.