Programmable application specific integrated circuit and logic cell therefor

Claim 2

A field programmable gate array comprising a logic cell, the logic cell comprising: a first multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead; a second multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead; a third multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, the first data input lead of the third multiplexer being coupled to the output lead of the first multiplexer, the second data input lead of the third multiplexer being coupled to the output lead of the second multiplexer; a first gate having a plurality of input leads and an output lead, the output lead of the first gate being coupled to the select input lead of the first multiplexer; a second gate having a plurality of input leads and an output lead, the output lead of the second gate being coupled to the select input lead of the third multiplexer; a third gate having an output lead, the output lead of the third gate being coupled to the first data input lead of the first multiplexer; a fourth gate having an output lead, the output lead of the fourth gate being coupled to the second data input lead of the first multiplexer; a fifth gate having an output lead, the output lead of the fifth gate being coupled to the first data input lead of the second multiplexer; a sixth gate having an output lead, the output lead of the sixth gate being coupled to the second data input lead of the second multiplexer; and a sequential logic element having a data input lead and a clear input lead, the data input lead of the sequential logic element being coupled to the output lead of the third multiplexer, the clear input lead of the sequential logic element being electrically isolated from all of the input leads of the first gate and from all of the input leads of the second gate.

Claim 3

A field programmable gate array comprising a logic cell, the logic cell comprising: a first field effect transistor having a first electrode, a second electrode and a gate electrode; a second field effect transistor having a first electrode, a second electrode and a gate electrode, the second electrode of the second field effect transistor being coupled to the second electrode of the first field effect transistor; a third field effect transistor having a first electrode, a second electrode and a gate electrode; a fourth field effect transistor having a first electrode, a second electrode and a gate electrode, the second electrode of the fourth field effect transistor being coupled to the second electrode of the third field effect transistor; a first inverter having an input lead and an output lead, the output lead of the inverter being coupled to the gate electrode of the second field effect transistor and being coupled to the gate electrode of the fourth field effect transistor, the input lead of the first inverter being coupled to the gate electrode of the first field effect transistor and being coupled to the gate electrode of the third field effect transistor; a first gate having a plurality of input leads and an output lead, the output lead of the first gate being coupled to the input lead of the first inverter; a fifth field effect transistor having a first electrode, a second electrode and a gate electrode, the first electrode of the fifth field effect transistor being coupled to the second electrode of the first field effect transistor; a sixth field effect transistor having a first electrode, a second electrode and a gate electrode, the first electrode of the sixth field effect transistor being coupled to the second electrode of the third field effect transistor, the second electrode of the sixth field effect transistor being coupled to the second electrode of the fifth field effect transistor; a second inverter having an input lead and an output lead, the output lead of the second inverter being coupled to the gate electrode of the sixth field effect transistor, the input lead of the second inverter being coupled to the gate electrode of the fifth field effect transistor; a second gate having a plurality of input leads and an output lead, the output lead of the second gate being coupled to the input lead of the second inverter; a sequential logic element having a data input lead and a clear input lead, the data input lead being coupled to the second electrode of the fifth field effect transistor, the clear input lead being electrically isolated from all of the input leads of the first gate and from all of the input leads of the second gate; a third gate having an output lead, the output lead of the third gate being coupled to the first electrode of the first field effect transistor; a fourth gate having an output lead, the output lead of the fourth gate being coupled to the first electrode of the second field effect transistor; a fifth gate having an output lead, the output lead of the fifth gate being coupled to the first electrode of the third field effect transistor; and a sixth gate having an output lead, the output lead of the sixth gate being coupled to the first electrode of the fourth field effect transistor.

Claim 4

A field programmable gate array comprising a logic cell, the logic cell comprising: a first field effect transistor having a first electrode, a second electrode and a gate electrode; a second field effect transistor having a first electrode, a second electrode and a gate electrode, the second electrode of the second field effect transistor being coupled to the second electrode of the first field effect transistor; a third field effect transistor having a first electrode, a second electrode and a gate electrode; a fourth field effect transistor having a first electrode, a second electrode and a gate electrode, the second electrode of the fourth field effect transistor being coupled to the second electrode of the third field effect transistor; a first inverter having an input lead and an output lead, the output lead of the inverter being coupled to the gate electrode of the second field effect transistor and being coupled to the gate electrode of the fourth field effect transistor, the input lead of the first inverter being coupled to the gate electrode of the first field effect transistor and being coupled to the gate electrode of the third field effect transistor; a first gate having a plurality of input leads and an output lead, the output lead of the first gate being coupled to the input lead of the first inverter; a fifth field effect transistor having a first electrode, a second electrode and a gate electrode, the first electrode of the fifth field effect transistor being coupled to the second electrode of the first field effect transistor; a sixth field effect transistor having a first electrode, a second electrode and a gate electrode, the first electrode of the sixth field effect transistor being coupled to the second electrode of the third field effect transistor, the second electrode of the sixth field effect transistor being coupled to the second electrode of the fifth field effect transistor; a second inverter having an input lead and an output lead, the output lead of the second inverter being coupled to the gate electrode of the sixth field effect transistor, the input lead of the second inverter being coupled to the gate electrode of the fifth field effect transistor; a second gate having a plurality of input leads and an output lead, the output lead of the second gate being coupled to the input lead of the second inverter; a sequential logic element having a data input lead and a clear input lead, the data input lead being coupled to the second electrode of the fifth field effect transistor, the clear input lead being electrically isolated from all of the input leads of the first gate and from all of the input leads of the second gate; a third gate having an output lead, the output lead of the third gate being coupled to the first electrode of the first field effect transistor; a fourth gate having an output lead, the output lead of the fourth gate being coupled to the first electrode of the second field effect transistor; a fifth gate having an output lead, the output lead of the fifth gate being coupled to the first electrode of the third field effect transistor; and a sixth gate having an output lead, the output lead of the sixth gate being coupled to the first electrode of the fourth field effect transistor.