US5594926A — Hard disk accelerating system for computer

Claim 1

Independent Claim 405 words

A hard disk accelerating system for a computer that contains a hard disk drive, a system memory, and a central processing unit ("CPU") for generating input-output ("IO") read/memory write cycles to transfer data from the hard drive to the system memory and for generating memory read/IO write cycles to transfer data from the system memory to the hard drive, the hard drive being divided into sectors and having a hard-drive data register, the CPU and system memory being coupled to a first bus, the hard drive being coupled to a second bus that operates at a lower clock rate than the first bus, the accelerating system comprising the following elements for decomposing disk access operation for each of read and write into at least two tasks which can be executed concurrently: a read buffer for storing data received from the hard drive; a write buffer for storing data to be moved to the hard drive; and a control and state machine that comprises (a) a word counter for keeping track of the number of data words moved into the read buffer from the hard drive since the accelerating system began to read a sector of the hard drive; (b) a first address register for pointing to a unit of the read buffer for storing the incoming data from the hard drive; (c) a second address register for pointing to a unit of the read buffer for the CPU to access; (d) an address latch register for latching the address of the hard-drive data register; (e) a plurality of buffer status flags for tracking the status of the read buffer; and (f) a state machine for monitoring IO operations performed on the hard drive, determining when to start, suspend, resume, and end fetching data from a sector of the hard drive, generating hard drive read cycles to read data from the hard drive, causing data to be transferred from the hard drive to the read buffer during a hard drive read cycle concurrently while data is being transferred from the read buffer to the system memory during a prior IO read/memory write cycle, generating hard drive write cycles to write data to the hard drive, and causing data to be transferred from the write buffer to the hard drive during a hard drive write cycle concurrently while data is being transferred from the system memory to the write buffer during a subsequent memory read/IO write cycle.

Claim 2

Dependent Claim 405 words

A hard disk accelerating system for a computer that contains a hard disk drive, a system memory, and a central processing unit ("CPU") for generating input-output ("IO") read/memory write cycles to transfer data from the hard drive to the system memory and for generating memory read/IO write cycles to transfer data from the system memory to the hard drive, the hard drive being divided into sectors and having a hard-drive data register, the CPU and system memory being coupled to a first bus, the hard drive being coupled to a second bus that operates at a lower clock rate than the first bus, the accelerating system comprising the following elements for decomposing disk access operation for each of read and write into at least two tasks which can be executed concurrently: a read buffer for storing data received from the hard drive; a write buffer for storing data to be moved to the hard drive; and a control and state machine that comprises (a) a word counter for keeping track of the number of data words moved into the read buffer from the hard drive since the accelerating system began to read a sector of the hard drive; (b) a first address register for pointing to a unit of the read buffer for storing the incoming data from the hard drive; (c) a second address register for pointing to a unit of the read buffer for the CPU to access; (d) an address latch register for latching the address of the hard-drive data register; (e) a plurality of buffer status flags for tracking the status of the read buffer; and (f) a state machine for monitoring IO operations performed on the hard drive, determining when to start, suspend, resume, and end fetching data from a sector of the hard drive, generating hard drive read cycles to read data from the hard drive, causing data to be transferred from the hard drive to the read buffer during a hard drive read cycle concurrently while data is being transferred from the read buffer to the system memory during a prior IO read/memory write cycle, generating hard drive write cycles to write data to the hard drive, and causing data to be transferred from the write buffer to the hard drive during a hard drive write cycle concurrently while data is being transferred from the system memory to the write buffer during a subsequent memory read/IO write cycle.

Claim 3

Dependent Claim 15 words

An accelerating system as in claim 1 wherein the read buffer comprises a first-in-first-out buffer.

Claim 4

Dependent Claim 31 words

An accelerating system as in claim 1 wherein the read buffer is at least twice the bit size of an IO command needed to improve the hard disk data transfer speed.

Claim 5

Dependent Claim 62 words

An accelerating system as in claim 1 wherein the read buffer is at least 32 bits wide, and comprises at least two 16-bit units to support 16-bit IO commands so that, while the CPU is accessing data from one of the 16-bit units, the state machine can read data from the hard drive and store it into another of the 16-bit units.

Claim 6

Dependent Claim 16 words

An accelerating system as in claim 1 wherein the accelerating system is coupled to the buses.

Claim 7

Dependent Claim 30 words

An accelerating system as in claim 5 wherein the first bus is a CPU system bus, and the second bus is an industry standard architecture ("ISA") advanced technology ("AT") bus.

Claim 8

Dependent Claim 22 words

An accelerating system as in claim 6 wherein the system complies to the American National Standard for Information Systems AT Attachment Specification.

Claim 9

Dependent Claim 26 words

An accelerating system as in claim 7 further including an integrated device electronics ("IDE") IO controller coupled between the hard drive and the ISA AT bus.

Claim 10

Dependent Claim 20 words

An accelerating system as in claim 8 wherein the IDE IO controller comprises a conventional ISA hard disk controller card.

Claim 11

Dependent Claim 34 words

An accelerating system as in claim 6 further including logic means for suspending hard drive cycles for at least one of a normal AT cycle, a hidden refresh cycle, and a CPU hold cycle.

Claim 12

Dependent Claim 31 words

An accelerating system as in claim 6 further including a programmable hardware register for adjusting the hard disk read or write cycle time from 2 AT clocks to 5 AT clocks.

Claim 13

Dependent Claim 14 words

An accelerating system as in claim 11 wherein the hardware register is software programmable.

Claim 14

Dependent Claim 47 words

An accelerating system as in claim 1 wherein: each hard drive read cycle is part of an overall read cycle that includes an IO read/memory write cycle; and each hard drive write cycle is part of an overall write cycle that includes a memory read/IO write cycle.

Claim 15

Dependent Claim 91 words

An accelerating system as in claim 13 wherein: each IO read/memory write cycle comprises (a) an IO read cycle during which data is transferred from the read buffer to the CPU and (b) a memory write cycle during which data is transferred from the CPU to the system memory; and each memory read/IO write cycle comprises (a) a memory read cycle during which data is transferred from the system memory to the CPU and (b) an IO write cycle during which data is transferred from the CPU to the write buffer.

Claim 16

Dependent Claim 60 words

An accelerating system as in claim 13 wherein the read buffer comprises at least two read units controlled so that the state machine causes data to be transferred from the hard drive to one of the read units concurrently while the CPU is accessing data from another of the read units to transfer the so-accessed data to the system memory.

Claim 17

Dependent Claim 309 words

A hard drive accelerating system for a computer that contains a hard disk drive, a system memory, and a central processing unit ("CPU") which (a) generates input-output ("IO") read/memory write cycles for transferring data from the hard drive to the system memory and (b) generates memory read/IO write cycles for transferring data from the system memory to the hard drive, the CPU and the system memory being coupled to a first bus, the hard drive being coupled to a second bus that operates at a lower clock rate than the first bus, the accelerating system comprising: a read buffer for storing data received from the hard drive; a write buffer for storing data to be transferred to the hard drive; and a state machine (a) for generating hard drive read cycles each being part of an overall read cycle that includes an IO read/memory write cycle generated by the CPU, (b) for causing data to be transferred from the hard drive to the read buffer by way of the second bus during the hard drive read cycle of an overall read cycle concurrently while data is being transferred from the read buffer to the system memory by way of the first bus during the IO read/memory write cycle of at least one prior overall read cycle, (c) for generating hard drive write cycles each being part of an overall write cycle that includes a memory read/IO write cycle generated by the CPU, and (d) for causing data to be transferred from the write buffer to the hard drive by way of the second bus during the hard drive write cycle of an overall write cycle concurrently while data is being transferred from the system memory to the write buffer by way of the first bus during the memory read/IO write cycle of at least one subsequent overall write cycle.

Claim 18

Dependent Claim 309 words

A hard drive accelerating system for a computer that contains a hard disk drive, a system memory, and a central processing unit ("CPU") which (a) generates input-output ("IO") read/memory write cycles for transferring data from the hard drive to the system memory and (b) generates memory read/IO write cycles for transferring data from the system memory to the hard drive, the CPU and the system memory being coupled to a first bus, the hard drive being coupled to a second bus that operates at a lower clock rate than the first bus, the accelerating system comprising: a read buffer for storing data received from the hard drive; a write buffer for storing data to be transferred to the hard drive; and a state machine (a) for generating hard drive read cycles each being part of an overall read cycle that includes an IO read/memory write cycle generated by the CPU, (b) for causing data to be transferred from the hard drive to the read buffer by way of the second bus during the hard drive read cycle of an overall read cycle concurrently while data is being transferred from the read buffer to the system memory by way of the first bus during the IO read/memory write cycle of at least one prior overall read cycle, (c) for generating hard drive write cycles each being part of an overall write cycle that includes a memory read/IO write cycle generated by the CPU, and (d) for causing data to be transferred from the write buffer to the hard drive by way of the second bus during the hard drive write cycle of an overall write cycle concurrently while data is being transferred from the system memory to the write buffer by way of the first bus during the memory read/IO write cycle of at least one subsequent overall write cycle.

Claim 19

Dependent Claim 49 words

An accelerating system as in claim 19 wherein each IO read/memory write cycle comprises (a) an IO read cycle during which data is transferred from the read buffer to the CPU and (b) a memory write cycle during which data is transferred from the CPU to the system memory.

Claim 20

Dependent Claim 49 words

An accelerating system as in claim 19 wherein the read buffer comprises at least two read units controlled so that data is transferred from the hard drive to one of the read units concurrently while data is being transferred from another of the read units to the system memory.

Claim 21

Dependent Claim 49 words

An accelerating system as in claim 16 wherein each memory read/IO write cycle comprises (a) a memory read cycle during which data is transferred from the system memory to the CPU and (b) an IO write cycle during which data is transferred from the CPU to the write buffer.

Claim 22

Dependent Claim 44 words

An accelerating system as in claim 16 wherein data is transferred from the write buffer to the hard drive during an overall write cycle concurrently while data is being transferred from the system memory to the write buffer during the next overall write cycle.

Claim 23

Dependent Claim 91 words

An accelerating system as in claim 16 wherein: each IO read/memory write cycle comprises (a) an IO read cycle during which data is transferred from the read buffer to the CPU and (b) a memory write cycle during which data is transferred from the CPU to the system memory; and each memory read/IO write cycle comprises (a) a memory read cycle during which data is transferred from the system memory to the CPU and (b) an IO write cycle during which data is transferred from the CPU to the write buffer.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-01-14	2000-07-15	2001-01-14	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-01-14	2004-07-15	2005-01-14	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-01-14	2008-07-15	2009-01-14	$7700.00	Window Closed / Lapsed

Hard disk accelerating system for computer

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