Patent US5598545A successfully refreshed from Google Patents.
US5598545A
Expired / Lapsed
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Circuitry and method for performing two operating instructions during a single clock in a processing device
Assignee: Texas Instruments Inc
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Filing: 1993-03-25
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Granted: 1997-01-28
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Expires: 2013-03-25
Abstract
Abstract Circuitry and method for performing a double instruction during a single clock cycle in a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The circuitry includes four sense amps per processor element and one ALU to enable reading of four data bits per clock cycle. The method includes reading data from each register file in a processor element and writing the data in one of the register file memory banks; enabling a 2:1 reduction in the amount of required instructions and a substantial reduction in overall cycle time.
Inventors
- 👤 Jim Childers
- 👤 Peter Reinecke
- 👤 Yutaka Takahashi
- 👤 Seiichi Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06F15/8053; G06F15/8092; G06F9/30007; G06F9/30032; G06F9/30098; G06F9/3012; G06F9/30134; G06F9/30141; G06F9/38; G06F9/3836; G06F9/3853; G06F9/3885; G06F9/3887; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
127 words
A method for performing two instructions in parallel in a processing element including a single instruction arithmetic and logic unit (ALU) and addressable storage locations, the method comprising the steps of: (a) reading simultaneously a first and second data pair from said storage locations addressed respectively by a first and second of said instructions; a first portion of each said data pair being stored in consecutively addressed of said storage locations; a second portion of each said data pair being stored in consecutively addressed of said storage locations; (b) operating upon said first data pair and obtaining a result with said ALU; (c) repeating step (b) for said second data pair; and, (d) writing results obtained from steps (b) and (c) into respective of said storage locations.
Claim 2
Independent Claim
127 words
A method for performing two instructions in parallel in a processing element including a single instruction arithmetic and logic unit (ALU) and addressable storage locations, the method comprising the steps of: (a) reading simultaneously a first and second data pair from said storage locations addressed respectively by a first and second of said instructions; a first portion of each said data pair being stored in consecutively addressed of said storage locations; a second portion of each said data pair being stored in consecutively addressed of said storage locations; (b) operating upon said first data pair and obtaining a result with said ALU; (c) repeating step (b) for said second data pair; and, (d) writing results obtained from steps (b) and (c) into respective of said storage locations.
Claim 3
Dependent Claim
22 words
The method of claim 1, wherein said steps (b) and (c) comprise the step of: performing identical arithmetic operations on the data.
Claim 4
Dependent Claim
82 words
The method of claim 1, further comprising the step of performing steps (a) through (d) during a single clock cycle, said clock cycle including the sequence of reading data from said first and second data pair; latching said first data pair into said ALU; operating on said first data pair in said ALU; latching said second data pair in said ALU; operating on said second data pair in said ALU; and, writing results from said operations in respective of said storage locations.
Claim 5
Dependent Claim
20 words
The method of claim 1, step (b) including the step of first: latching said first data pair into said ALU.
Claim 6
Dependent Claim
57 words
The method of claim 1, said first data pair comprising lesser significant bits of a string, and said second data pair comprising next more significant bits of said string as compared to said first data pair; said step (b) resulting in a first carry; performing said step (c) with said second data pair and said first carry.
Claim 7
Dependent Claim
56 words
The method of claim 5, prior to step (a), said processing device operating on an initial data pair resulting in an initial carry; said initial data pair comprising next less significant bits of said string as compared to said first data pair; said step (b) including operating with said first data pair and said initial carry.
Claim 8
Dependent Claim
97 words
In a processing element including an arithmetic and logic unit (ALU) and storage including addressable storage locations for storing data; a method for processing a sequence of instructions simultaneously including the steps of: a) reading simultaneously contents of multiple of said storage locations addressed by said sequence of instructions; b) operating on a portion of said contents of step (a) accessed through one of said sequence of instructions and generating a result in said ALU; and c) repeating step (b) until all said contents of step (a) have been operated upon without re-reading from said storage locations.
Claim 9
Dependent Claim
97 words
In a processing element including an arithmetic and logic unit (ALU) and storage including addressable storage locations for storing data; a method for processing a sequence of instructions simultaneously including the steps of: a) reading simultaneously contents of multiple of said storage locations addressed by said sequence of instructions; b) operating on a portion of said contents of step (a) accessed through one of said sequence of instructions and generating a result in said ALU; and c) repeating step (b) until all said contents of step (a) have been operated upon without re-reading from said storage locations.
Claim 10
Dependent Claim
23 words
The method of claim 7, said method including: d) simultaneously writing each of the results of steps (b) and (c) into said storage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-28 | 2000-07-29 | 2001-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-28 | 2004-07-29 | 2005-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-28 | 2008-07-29 | 2009-01-28 | $7700.00 | Window Closed / Lapsed |