Dynamic redundancy circuit for memory in integrated circuit form

Claim 2

An electrically programmable and erasable non-volatile integrated circuit memory, comprising: a plurality of memory words, each word corresponding to an address; means for accessing a memory word of the plurality of words in response to the memory receiving an input address; a dynamically programmable auxiliary memory for storing addresses of defective memory words; a comparison circuit for comparing the input address with an address stored in the dynamically programmable auxiliary memory; and a readressing circuit for selecting another memory word from the plurality of memory words in response to the comparison circuit detecting that the input address matches an address stored in the dynamically programmable auxiliary memory; wherein the dynamically programmable auxiliary memory includes a valid bit for each stored address to indicate whether the stored address is valid, and wherein the plurality of memory words includes a second plurality of supplementary memory words that are addressable through the readressing circuit only and not through the means for accessing.

Claim 3

The memory of claim 1 wherein the comparison circuit is implemented as a programmable logic array.

Claim 4

The memory of claim 1 wherein the memory words are arranged according to a row address and a column address and wherein the memory includes a row decoder, receiving a plurality of bits of the input address, and a column decoder, receiving a second plurality of bits of the input address, to address the memory word corresponding to the input address, and wherein the readressing circuit causes the row decoder and the column decoder to address a supplementary memory word of the memory, when the comparison circuit detects that the input address matches a address stored in the dynamically programmable auxiliary memory.

Claim 5

The memory of claim 1 wherein the comparison circuit includes means for successively reading through the addresses stored in the dynamically programmable auxiliary memory to compare the addresses stored in the dynamically programmable auxiliary memory with the input address.

Claim 6

The memory of claim 1 wherein the comparison circuit has means for simultaneously reading all the addresses stored in the dynamically programmable auxiliary memory and means for simultaneously comparing all the addresses stored in the dynamically programmable auxiliary memory with the input address to detect if the input address matches one of the addresses stored in the dynamically programmable auxiliary memory.

Claim 7

The memory of claim 1 wherein the dynamically programmable auxiliary memory includes stored addresses of defective memory words, the stored addresses being stored during operation of the memory.

Claim 8

The memory of claim 1 further comprising a verification circuit, coupled to the plurality of memory words and the dynamically programmable auxiliary memory, for determining whether one of the plurality of memory words is defective, the verification circuit providing an address of the defective one of the plurality of memory words to the dynamically programmable auxiliary memory.

Claim 9

The memory of claim 7 wherein the verification circuit includes: a dynamic memory, coupled to the plurality of memory words and storing a data in response to the data being written to a content of one of the plurality of memory words; and a comparison circuit, coupled to the dynamic memory and the plurality of memory words, for comparing the content of the one of the plurality of words with the data stored in the dynamic memory, the comparison circuit determining that the one of the plurality of memory words is defective when the content of the one of the plurality of memory words is not identical to the data stored in the dynamic memory.

Claim 10

A memory, comprising: a plurality of memory words, each word corresponding to an address; means for accessing a memory word of the plurality of words in response to the memory receiving an input address; a dynamically programmable auxiliary memory for holding addresses of defective memory words; means for comparing the input address with the addresses stored in the dynamically programmable auxiliary memory; and means for causing the means for accessing to access a supplemental memory word, rather than a corresponding memory word, if the means for comparing detects that the input address matches an address stored in the dynamically programmable auxiliary memory; wherein the dynamically programmable auxiliary memory includes a valid bit for each stored address to indicate whether the stored address is valid and wherein the means for comparing indicates a match only if the valid bit indicates that the stored address is valid.

Claim 11

A memory, comprising: a plurality of memory words, each word corresponding to an address; means for accessing a memory word of the plurality of words in response to the memory receiving an input address; a dynamically programmable auxiliary memory for holding addresses of defective memory words; means for comparing the input address with the addresses stored in the dynamically programmable auxiliary memory; and means for causing the means for accessing to access a supplemental memory word, rather than a corresponding memory word, if the means for comparing detects that the input address matches an address stored in the dynamically programmable auxiliary memory; wherein the dynamically programmable auxiliary memory includes a valid bit for each stored address to indicate whether the stored address is valid and wherein the means for comparing indicates a match only if the valid bit indicates that the stored address is valid.

Claim 12

The memory of claim 9 wherein the means for comparing includes means for successively reading through the addresses stored in the dynamically programmable auxiliary memory and for successively comparing the addresses stored in the dynamically programmable auxiliary memory with the input address.

Claim 13

The memory of claim 9 wherein the means for comparing includes means for simultaneously reading all of the addresses stored in the dynamically programmable auxiliary memory and for simultaneously comparing all of the addresses stored in the dynamically programmable auxiliary memory with the input address to detect at that the input address matches one of the addresses stored in the dynamically programmable auxiliary memory.

Claim 14

The memory of claim 9 wherein the memory words are arranged in an array that is addresses by a row address and a column address, the memory further comprising a row decoder receiving a first plurality of bits of the input address and a column decoder receiving a second plurality of bits of the input address, the row and column decoder addressing the memory array to provide the memory word corresponding to the input address.

Claim 15

The memory of claim 12 wherein the means for comparing has means for disabling the row decoder if the input address matches an address stored in the dynamically programmable auxiliary memory and wherein the readressing circuit has means for selecting a supplemental row of the array if the means for comparing detects that the input address matches an address stored in the dynamically programmable auxiliary memory.

Claim 16

The memory of claim 9 wherein the dynamically programmable auxiliary memory includes stored addresses of defective memory words, the stored addresses being stored during operation of the memory.

Claim 17

The memory of claim 9 further comprising a verification circuit, coupled to the plurality of memory words and the dynamically programmable auxiliary memory, for determining whether one of the plurality of memory words is defective, the verification circuit providing an address of the defective one of the plurality of memory words to the dynamically programmable auxiliary memory.

Claim 18

The memory of claim 15 wherein the verification circuit includes: a dynamic memory, coupled to the plurality of memory words and storing a data in response to the data being written to a content of one of the plurality of memory words; and a comparison circuit, coupled to the dynamic memory and the plurality of memory words, for comparing the content of the one of the plurality of words with the data stored in the dynamic memory, the comparison circuit determining that the one of the plurality of memory words is defective when the content of the one of the plurality of memory words is not identical to the data stored in the dynamic memory.

Claim 21

The method of claim 17 wherein the step (a) of comparing includes comparing the input addresses with addresses that were stored in the dynamically programmable auxiliary memory during operation of the memory.

Claim 22

The method of claim 17 wherein the step (a) of comparing includes the steps of: simultaneously reading all addresses stored in the dynamically programmable auxiliary memory; and simultaneously comparing all of the addresses stored in the dynamically programmable auxiliary memory with the input address.

Claim 23

The method of claim 17 wherein the step (a) of comparing includes the steps of: successively reading through the addresses stored in the dynamically programmable auxiliary memory to compare each of the addresses with the input address.

Claim 24

An electrically programmable and erasable non-volatile integrated circuit memory, comprising: a plurality of memory words, each word corresponding to an address; means for accessing a memory word of the plurality of words in response to the memory receiving an input address; an auxiliary memory for storing addresses of defective memory words; a comparison circuit for simultaneously comparing the input address with the addresses stored in the auxiliary memory; and a readressing circuit for selecting another memory word from the plurality of memory words in response to the comparison circuit detecting that the input address matches an address stored in the auxiliary memory; wherein the auxiliary memory includes a valid bit for each stored address to indicate whether the stored address is valid, .and wherein the plurality of memory words includes a second plurality of supplementary memory words that are addressable through the readressing circuit only and not through the means for accessing.

Claim 25

An electrically programmable and erasable non-volatile integrated circuit memory, comprising: a plurality of memory words, each word corresponding to an address; means for accessing a memory word of the plurality of words in response to the memory receiving an input address; an auxiliary memory for storing addresses of defective memory words; a comparison circuit for simultaneously comparing the input address with the addresses stored in the auxiliary memory; and a readressing circuit for selecting another memory word from the plurality of memory words in response to the comparison circuit detecting that the input address matches an address stored in the auxiliary memory; wherein the auxiliary memory includes a valid bit for each stored address to indicate whether the stored address is valid, .and wherein the plurality of memory words includes a second plurality of supplementary memory words that are addressable through the readressing circuit only and not through the means for accessing.

Claim 26

The memory of claim 21 wherein the memory words are arranged according to a row address and a column address and wherein the memory includes a row decoder, receiving a plurality of bits of the input address, and a column decoder, receiving a second plurality of bits of the input address, to address the memory word corresponding to the input address, and wherein the readressing circuit causes the row decoder and the column decoder to address a supplementary memory word of the memory, when the comparison circuit detects that the input address matches a address stored in the auxiliary memory.

Claim 27

A memory, comprising: a plurality of memory words, each word corresponding to an address; means for accessing a memory word of the plurality of words in response to the memory receiving an input address; an auxiliary memory for holding addresses of defective memory words; means for simultaneously comparing the input address with the addresses stored in the auxiliary memory; and means for causing the means for accessing to access a supplemental memory word, rather than a corresponding memory word, if the means for simultaneously comparing detects that the input address matches an address stored in the auxiliary memory; wherein the auxiliary memory includes a valid bit for each stored address to indicate whether the stored address is valid and wherein the means for comparing indicates a match only if the valid bit indicates that the stored address is valid.

Claim 28

A memory, comprising: a plurality of memory words, each word corresponding to an address; means for accessing a memory word of the plurality of words in response to the memory receiving an input address; an auxiliary memory for holding addresses of defective memory words; means for simultaneously comparing the input address with the addresses stored in the auxiliary memory; and means for causing the means for accessing to access a supplemental memory word, rather than a corresponding memory word, if the means for simultaneously comparing detects that the input address matches an address stored in the auxiliary memory; wherein the auxiliary memory includes a valid bit for each stored address to indicate whether the stored address is valid and wherein the means for comparing indicates a match only if the valid bit indicates that the stored address is valid.

Claim 29

The memory of claim 23 wherein the memory words are arranged in an array that is addresses by a row address and a column address, the memory further comprising a row decoder receiving a first plurality of bits of the input address and a column decoder receiving a second plurality of bits of the input address, the row and column decoder addressing the memory array to provide the memory word corresponding to the input address.

Claim 32

A memory, comprising: a plurality of memory words, each word corresponding to an address; means for accessing a memory word of the plurality of words in response to the memory receiving an input address; a dynamically programmable auxiliary memory for holding addresses of defective memory words; means for comparing the input address with the addresses stored in the dynamically programmable auxiliary memory; means for causing the means for accessing to access a supplemental memory word, rather than a corresponding memory word, if the means for comparing detects that the input address matches an address stored in the dynamically programmable auxiliary memory; and a verification circuit, coupled to the plurality of memory words and the dynamically programmable auxiliary memory, for determining whether one of the plurality of memory words is defective, the verification circuit providing an address of the defective one of the plurality of memory words to the dynamically programmable auxiliary memory, the verification circuit including: a dynamic memory, coupled to the plurality of memory words and storing a data in response to the data being written to a content of one of the plurality of memory words; and a comparison circuit, coupled to the dynamic memory and the plurality of memory words, for comparing the content of the one of the plurality of words with the data stored in the dynamic memory, the comparison circuit determining that the one of the plurality of memory words is defective when the content of the one of the plurality of memory words is not identical to the data stored in the dynamic memory.

Claim 33

A memory, comprising: a plurality of memory words, each word corresponding to an address; means for accessing a memory word of the plurality of words in response to the memory receiving an input address; a dynamically programmable auxiliary memory for holding addresses of defective memory words; means for comparing the input address with the addresses stored in the dynamically programmable auxiliary memory; means for causing the means for accessing to access a supplemental memory word, rather than a corresponding memory word, if the means for comparing detects that the input address matches an address stored in the dynamically programmable auxiliary memory; and a verification circuit, coupled to the plurality of memory words and the dynamically programmable auxiliary memory, for determining whether one of the plurality of memory words is defective, the verification circuit providing an address of the defective one of the plurality of memory words to the dynamically programmable auxiliary memory, the verification circuit including: a dynamic memory, coupled to the plurality of memory words and storing a data in response to the data being written to a content of one of the plurality of memory words; and a comparison circuit, coupled to the dynamic memory and the plurality of memory words, for comparing the content of the one of the plurality of words with the data stored in the dynamic memory, the comparison circuit determining that the one of the plurality of memory words is defective when the content of the one of the plurality of memory words is not identical to the data stored in the dynamic memory.

Claim 34

The memory of claim 26 wherein the means for comparing includes means for successively reading through the addresses stored in the dynamically programmable auxiliary memory and for successively comparing the addresses stored in the dynamically programmable auxiliary memory with the input address.

Claim 35

The memory of claim 26 wherein the means for comparing includes means for simultaneously reading all of the addresses stored in the dynamically programmable auxiliary memory and for simultaneously comparing all of the addresses stored in the dynamically programmable auxiliary memory with the input address to detect at that the input address matches one of the addresses stored in the dynamically programmable auxiliary memory.

Claim 36

The memory of claim 26 wherein the memory words are arranged in an array that is addresses by a row address and a column address, the memory further comprising a row decoder receiving a first plurality of bits of the input address and a column decoder receiving a second plurality of bits of the input address, the row and column decoder addressing the memory array to provide the memory word corresponding to the input address.

Claim 37

The memory of claim 29 wherein the means for comparing has means for disabling the row decoder if the input address matches an address stored in the dynamically programmable auxiliary memory and wherein the readressing circuit has means for selecting a supplemental row of the array if the means for comparing detects that the input address matches an address stored in the dynamically programmable auxiliary memory.

Claim 38

The memory of claim 26 wherein the dynamically programmable auxiliary memory includes stored addresses of defective memory words, the stored addresses being stored during operation of the memory.

Claim 39

A memory circuit comprising: a plurality of memory cells; an auxiliary memory having a plurality of locations, at least one of the plurality of locations storing an address of a defective memory cell of the plurality of memory cells, the auxiliary memory further storing a valid bit for each of the plurality of locations that is active when an address stored in the respective location represents a defective cell of the plurality of memory cells; a comparison circuit, coupled to the auxiliary memory, having an input that receives an input address and an output that provides a supplemental address and a defect detection signal that is active when the input address does not match any of the addresses of the defective memory cells having an active valid bit; and an address decoder, having a first input that receives the input address, a second input that receives the supplemental address, and a control input that receives the defect detection signal, the address decoder having an output that provides the input address to the plurality of memory cells when the defect detection signal is not active and that provides the supplemental address to the plurality of memory cells when the defect detection signal is active.

Claim 40

A memory circuit comprising: a plurality of memory cells; an auxiliary memory having a plurality of locations, at least one of the plurality of locations storing an address of a defective memory cell of the plurality of memory cells, the auxiliary memory further storing a valid bit for each of the plurality of locations that is active when an address stored in the respective location represents a defective cell of the plurality of memory cells; a comparison circuit, coupled to the auxiliary memory, having an input that receives an input address and an output that provides a supplemental address and a defect detection signal that is active when the input address does not match any of the addresses of the defective memory cells having an active valid bit; and an address decoder, having a first input that receives the input address, a second input that receives the supplemental address, and a control input that receives the defect detection signal, the address decoder having an output that provides the input address to the plurality of memory cells when the defect detection signal is not active and that provides the supplemental address to the plurality of memory cells when the defect detection signal is active.

Claim 41

The memory circuit of claim 32, wherein: the plurality of memory cells includes: a first plurality of memory cells, disposed in a plurality of columns and a plurality of rows, the first plurality of memory cells being addressable by the decoder only when the defect detection signal is not active; and a second plurality of memory cells, disposed in at least one row and a plurality of columns that correspond to the plurality of rows, the second plurality of memory cells being addressable by the decoder only when the defect detection signal is active; and the decoder further includes a row decoder having a first input that receives a portion of the input address, a second input that receives the defect detection signal, a first output that addresses one of the plurality of rows in response to the input address when the defect detection signal is not active, and a second output that addresses the at least one row when the defect detection signal is active.

Claim 42

The memory circuit of claim 32, further comprising a programming circuit having an input that receives a write address and data written to the write address in the plurality of memory cells, a second input that receives data stored in the write address in the plurality of memory cells, and an output that provides the write address to the auxiliary memory as a defective address when the data written to the write address does not match the data stored in the write address.

Claim 43

The memory circuit of claim 32, wherein the comparison circuit includes: a plurality of comparison devices, each of the plurality of comparison devices having a first input that receives the input address, a second input that receives a corresponding one of the addresses of the auxiliary memory, and an output that provides a signal indicative of whether the input address matches the corresponding address; and a logic circuit having a plurality of inputs each of which receives the output of a respective one of the plurality of comparison devices, and an output that provides the defect detection signal.

Claim 44

A memory circuit comprising: a plurality of memory cells; an auxiliary memory that stores addresses of defective memory cells of the plurality of memory cells; a comparison circuit, coupled to the auxiliary memory, having an input that receives an input address and an output that provides a supplemental address and a defect detection signal that is active when the input address does not match any of the addresses of the defective memory cells; an address decoder, having a first input that receives the input address, a second input that receives the supplemental address, and a control input that receives the defect detection signal, the address decoder having an output that provides the input address to the plurality of memory cells when the defect detection signal is not active and that provides the supplemental address to the plurality of memory cells when the defect detection signal is active; and a programming circuit having an input that receives a write address and data written to the write address in the plurality of memory cells, a second input that receives data stored in the write address in the plurality of memory cells, and an output that provides the write address to the auxialiary memory as a defective address when the data written to the write address does not match the data stored in the write address.

Claim 45

A memory circuit comprising: a plurality of memory cells; an auxiliary memory that stores addresses of defective memory cells of the plurality of memory cells; a comparison circuit, coupled to the auxiliary memory, having an input that receives an input address and an output that provides a supplemental address and a defect detection signal that is active when the input address does not match any of the addresses of the defective memory cells; an address decoder, having a first input that receives the input address, a second input that receives the supplemental address, and a control input that receives the defect detection signal, the address decoder having an output that provides the input address to the plurality of memory cells when the defect detection signal is not active and that provides the supplemental address to the plurality of memory cells when the defect detection signal is active; and a programming circuit having an input that receives a write address and data written to the write address in the plurality of memory cells, a second input that receives data stored in the write address in the plurality of memory cells, and an output that provides the write address to the auxialiary memory as a defective address when the data written to the write address does not match the data stored in the write address.

Claim 46

The memory circuit of claim 36, wherein: the plurality of memory cells includes: a first plurality of memory cells, disposed in a plurality of columns and a plurality of rows, the first plurality of memory cells being addressable by the decoder only when the defect detection signal is not active; and a second plurality of memory cells, disposed in at least one row and a plurality of columns that correspond to the plurality of rows, the second plurality of memory cells being addressable by the decoder only when the defect detection signal is active; and the decoder further includes a row decoder having a first input that receives a portion of the input address, a second input that receives the defect detection signal, a first output that addresses one of the plurality of rows in response to the input address when the defect detection signal is not active, and a second output that addresses the at least one row when the defect detection signal is active.

Claim 47

The memory circuit of claim 36, wherein the comparison circuit includes: a plurality of comparison devices, each of the plurality of comparison devices having a first input that receives the input address, a second input that receives a corresponding one of the addresses of the auxiliary memory, and an output that provides a signal indicative of whether the input address matches the corresponding address; and a logic circuit having a plurality of inputs each of which receives the output of a respective one of the plurality of comparison devices, and an output that provides the defect detection signal.

Claim 48

A memory circuit comprising: a plurality of memory cells; an auxiliary memory that stores addresses of defective memory cells of the plurality of memory cells; a comparison circuit, coupled to the auxiliary memory, having an input that receives an input address and an output that provides a supplemental address and a defect detection signal that is active when the input address does not match any of the addresses of the defective memory cells, the comparison circuit including: a plurality of comparison devices, each of the plurality of comparison devices having a first input that receives the input address, a second input that receives a corresponding one of the addresses of the auxiliary memory, and an output that provides a signal indicative of whether the input address matches the corresponding address; and a logic circuit having a plurality of inputs each of which receives the output of a respective one of the plurality of comparison devices, and an output that provides the defect detection signal; and an address decoder, having a first input that receives the input address, a second input that receives the supplemental address, and a control input that receives the defect detection signal, the address decoder having an output that provides the input address to the plurality of memory cells when the defect detection signal is not active and that provides the supplemental address to the plurality of memory cells when the defect detection signal is active.

Claim 49

A memory circuit comprising: a plurality of memory cells; an auxiliary memory that stores addresses of defective memory cells of the plurality of memory cells; a comparison circuit, coupled to the auxiliary memory, having an input that receives an input address and an output that provides a supplemental address and a defect detection signal that is active when the input address does not match any of the addresses of the defective memory cells, the comparison circuit including: a plurality of comparison devices, each of the plurality of comparison devices having a first input that receives the input address, a second input that receives a corresponding one of the addresses of the auxiliary memory, and an output that provides a signal indicative of whether the input address matches the corresponding address; and a logic circuit having a plurality of inputs each of which receives the output of a respective one of the plurality of comparison devices, and an output that provides the defect detection signal; and an address decoder, having a first input that receives the input address, a second input that receives the supplemental address, and a control input that receives the defect detection signal, the address decoder having an output that provides the input address to the plurality of memory cells when the defect detection signal is not active and that provides the supplemental address to the plurality of memory cells when the defect detection signal is active.

Claim 50

The memory circuit of claim 39, wherein: the plurality of memory cells includes: a first plurality of memory cells, disposed in a plurality of columns and a plurality of rows, the first plurality of memory cells being addressable by the decoder only when the defect detection signal is not active; and a second plurality of memory cells, disposed in at least one row and a plurality of columns that correspond to the plurality of rows, the second plurality of memory cells being addressable by the decoder only when the defect detection signal is active; and the decoder further includes a row decoder having a first input that receives a portion of the input address, a second input that receives the defect detection signal, a first output that addresses one of the plurality of rows in response to the input address when the defect detection signal is not active, and a second output that addresses the at least one row when the defect detection signal is active.

Claim 53

The method of claim 41, wherein the step of addressing a memory cell includes operating a decoder in a first mode to access the memory cell; and the step of addressing a supplemental memory cell includes operating the decoder in a second mode to access the supplemental memory cell.

Claim 56

The apparatus of claim 43, further comprising a decoder operable in a first mode and a second mode, and wherein: the means for addressing a memory cell includes means for operating the decoder in the first mode to access the memory cell; and the means for addressing a supplemental memory cell includes means for operating the decoder in the second mode to access the supplemental memory cell.