Flash memory with improved erasability and its circuitry

Claim 2

A flash memory comprising: a memory cell array in which a plurality of nonvolatile memory cells, that can be erased electrically, are set in an array; decoding units that decode a plurality of signals and access said memory cell array; and drive units each of which includes a first power terminal and a second power terminal, inputs the output of said decoding unit, and selectively outputs a voltage applied to said first power terminal or a voltage approximate to said voltage, and a voltage applied to said second power terminal or a voltage approximate to said voltage; said drive unit assuming a first operation mode, in which a first voltage is applied to said first power terminal and a second voltage that is lower than said first voltage is applied to said second power terminal, and a second operation mode, in which a third voltage is applied to said first power terminal and a fourth voltage that is higher than said third voltage is applied to said second power terminal; and selecting an output voltage depending on whether said first or second operation mode is specified wherein said drive unit includes: a first conductive well region (p- or n-type well) enclosed in a second conductive well region (n- or p-type well) formed on a first conductive substrate (p- or n-type substrate); a first conductive channel transistor formed in said second conductive well region (n- or p-type well); and a second conductive channel transistor formed in said first conductive well region (p- or n-type well).

Claim 3

A flash memory comprising: a memory cell array in which a plurality of nonvolatile memory cells, that can be erased electrically, are set in an array; decoding units that decode a plurality of signals and access said memory cell array, said decoding unit has two output terminals with opposite phases of reverse logic; and drive units each of which includes a first power terminal and a second power terminal, inputs the output of said decoding unit, and selectively outputs a voltage applied to said first power terminal or a voltage approximate to said voltage, and a voltage applied to said second power terminal or a voltage approximate to said voltage; said drive unit assuming a first operation mode, in which a first voltage is applied to said first power terminal and a second voltage that is lower than said first voltage is applied to said second power terminal, and a second operation mode, in which a third voltage is applied to said first power terminal and a fourth voltage that is higher than said third voltage is applied to said second power terminal; and selecting an output voltage depending on whether said first or second operation mode is specified, said drive unit includes a first conductive well region (p- or n-type well) enclosed in a second conductive well region (n-or p-type well) formed on a first conductive substrate (p- or n-type substrate), and two second conductive channel transistors formed in said first conductive well region (p- or n-type well); and said two output terminals of said decoding unit with opposite phases are connected to the gates of said two second conductive channel transistors.

Claim 4

A flash memory comprising: a memory cell array in which a plurality of nonvolatile memory cells, that can be erased electrically, are set in an array; decoding units that decode a plurality of signals and access said memory cell array, said decoding unit has two output terminals with opposite phases of reverse logic; and drive units each of which includes a first power terminal and a second power terminal, inputs the output of said decoding unit, and selectively outputs a voltage applied to said first power terminal or a voltage approximate to said voltage, and a voltage applied to said second power terminal or a voltage approximate to said voltage; said drive unit assuming a first operation mode, in which a first voltage is applied to said first power terminal and a second voltage that is lower than said first voltage is applied to said second power terminal, and a second operation mode, in which a third voltage is applied to said first power terminal and a fourth voltage that is higher than said third voltage is applied to said second power terminal; and selecting an output voltage depending on whether said first or second operation mode is specified, said drive unit includes a first conductive well region (p- or n-type well) enclosed in a second conductive well region (n-or p-type well) formed on a first conductive substrate (p- or n-type substrate), and two second conductive channel transistors formed in said first conductive well region (p- or n-type well); and said two output terminals of said decoding unit with opposite phases are connected to the gates of said two second conductive channel transistors.

Claim 5

A flash memory according to claim 1, wherein: said decoding units and said drive units constitute a row decoder for selecting a row in said memory cell array; said flash memory includes; a level change circuit for changing the level of a signal to be fed to asid decoding units; a drive unit power switching circuit for switching power supplies for said drive unit; a high-voltage supply unit for selectively supplying a positive voltage and a high voltage; and a negative-voltage supply unit for selectively supplying a zero voltage and a negative voltage; said positive voltage, high voltage, zero voltage, and negative voltage having such a relationship that said negative voltage <said zero voltage <said positive voltage <said high voltage; and said drive unit power switching circuit (278) supplies said positive voltage to said first power terminals of said drive units (274) and said zero voltage to said second power terminals thereof, so that data will be read from said memory cell array; supplies said high voltage to said first power terminals of said drive units (274) and said zero voltage to said second power terminals thereof, so that data will be written in said memory cell array, and supplies said negative voltage to said first power terminals of said drive units and said positive voltage to said second power terminals thereof, so that data will be erased from said memory cell array.

Claim 6

A flash memory according to claim 3, wherein said level change circuit has a first terminal to which the output of said high-voltage supply unit is supplied and a second terminal to which the output of said negative-voltage supply unit is supplied; and said level change circuit outputs voltage to be applied to said first terminal or voltage approximate to said voltage, when the input of said level change circuit is high (equal to or less than the output of said high-voltage supply unit, and outputs voltage to be applied to said second terminal or voltage approximate to said voltage, when said input is low (equal to or larger than the output of said negative-voltage supply unit).

Claim 7

A flash memory according to claim 3 or 4, wherein said drive unit power switching circuit comprises two level change circuits 25 and 26.

Claim 8

A flash memory according to claim 2, wherein: said decoding units and said drive units constitute a row decoder for selecting a row in said memory cell array; said flash memory includes; a level change circuit for changing the level of a signal to be fed to said decoding units; a drive unit power switching circuit for switching power supplies for said drive unit; a high-voltage supply unit for selectively supplying a positive voltage and a high voltage; and a negative-voltage supply unit for selectively supplying a zero voltage and a negative voltage; said positive voltage, high voltage, zero voltage, and negative voltage having such a relationship that said negative voltage<said zero voltage<said positive voltage<said high voltage; and said drive unit power switching circuit supplies said positive voltage to said first power terminals of said drive units and said zero voltage to said second power terminals thereof, so that data will be read from said memory cell array; supplies said high voltage to said first power terminals of said drive units and said zero voltage to said second power terminals thereof, so that data will be written in said memory cell array; and supplies said negative voltage to said first power terminals of said drive units and said positive voltage to said second power terminals thereof, so that data will be erased from said memory cell array.

Claim 9

A flash memory according to claim 6, wherein said level change circuit has a first terminal to which the output of said high-voltage supply unit is supplied and a second terminal to which the output of said negative-voltage supply unit is supplied; and said level change circuit outputs voltage to be applied to said first terminal or voltage approximate to said voltage, when the input of said level change circuit is high (equal to or less than the output of said high-voltage supply unit), and outputs voltage to be applied to said second terminal or voltage approximate to said voltage, when said input is low (equal to or larger than the output of said negative-voltage supply unit).

Claim 10

A flash memory according to claim 6 or 7, wherein said drive unit power switching circuit comprises two level change circuits.