Signal transfer circuit for synchronous memory device

Claim 2

A signal transfer circuit for a synchronous memory device which has memory cell arrays and the associated peripheral circuits, comprising: an input terminal for inputting a clock signal; internal address generation means for generating an internal address signal; multiplexing means for selectively transferring an external address signal and the internal address signal from said internal address generation means; multiplexing control means for controlling the operation of said multiplexing means in response to the clock signal from said input terminal; an internal circuit for generating a data signal in response to the external or internal address signal transferred by said multiplexing means; data output buffer means for buffering the data signal generated by said internal circuit and outputting the buffered data signal externally; output buffer control means for controlling the operation of said data output buffer means in response to the clock signal from said input terminal; switching means connected between said internal circuit and said data output buffer means, for performing a switching operation to transfer the data signal from said internal circuit to said data output buffer means; and switching control means for controlling the operation of said switching means in response to the clock signal from said input terminal.

Claim 3

A signal transfer circuit for a synchronous memory device, as set forth in claim 1, further comprising clock signal delay means connected to said input terminal, for delaying the clock signal from said input terminal and supplying the delayed clock signal to said output buffer control means, said switching control means and said multiplexing control means.

Claim 4

A signal transfer circuit for a synchronous memory device, as set forth in claim 2, wherein said clock signal delay means is adapted to delay the clock signal from said input terminal by n clocks after the external address signal is applied, where n is 1, 2, 3, . . . , .

Claim 5

A signal transfer circuit for a synchronous memory device, as set forth in claim 2, wherein said clock signal delay means is adapted to delay the delay signal from said input terminal in the case where the subsequent clock is generated before the data signal from said internal circuit based on the external address signal is arrived at said data output buffer means.

Claim 6

A signal transfer circuit for a synchronous memory device, as set forth in claim 1, wherein said multiplexing means includes: a first switching device connected between an input terminal for inputting the external address signal and said internal circuit; and a second switching device connected between said internal address generation means and said internal circuit.

Claim 7

A signal transfer circuit for a synchronous memory device, as set forth in claim 5, wherein each of said first and second switching devices includes a PMOS transistor and an NMOS transistor connected in parallel to each other.

Claim 8

A signal transfer circuit for a synchronous memory device, as set forth in claim 5, wherein said multiplexing control means is adapted to turn on said first switching device in response to the clock signal from said input terminal and to turn on said second switching device after a predetermined delay time, in an initial mode that the external address signal is applied, and to turn on only said second switching device in response to a delayed one of the clock signal from said input terminal in a burst mode that the internal address signal from said internal address generation means is applied.

Claim 9

A signal transfer circuit for a synchronous memory device, as set forth in claim 2, wherein said multiplexing control means includes: an odd number of first inverters connected in series between an output terminal of said clock signal delay means and a first node; a first NAND gate for NANDing the delayed clock signal from said clock signal delay means and a pulse signal at said first node; a second inverter for inverting an output signal from said first NAND gate; a delay circuit connected between said output terminal of said clock signal delay means and a second node; an odd number of third inverters connected in series between said second node and a third node; a second NAND gate for NANDing pulse signals at said second and third nodes; a fourth inverter for inverting an output signal from said second NAND gate; first PMOS and NMOS transistors connected in parallel between an output terminal of said second inverter and said multiplexing means; and second PMOS and NMOS transistors connected in parallel between an output terminal of said fourth inverter and said multiplexing means, said first and second PMOS and NMOS transistors being operated in response to a burst mode control signal.

Claim 10

A signal transfer circuit for a synchronous memory device, as set forth in claim 2, wherein said multiplexing control means includes: an odd number of first inverters connected in series between an output terminal of said clock signal delay means and a first node; a first NAND gate for NANDing the delayed clock signal from said clock signal delay means and a pulse signal at said first node; a second inverter for inverting an output signal from said first NAND gate; an odd number of third inverters connected in series between said output terminal of said clock signal delay means and a second node; a second NAND gate for NANDing the delayed clock signal from said clock signal delay means and a pulse signal at said second node; a fourth inverter for inverting an output signal from said second NAND gate; an odd number of fifth inverters connected in series between an input terminal for inputting a burst mode control signal and a third node; a third NAND gate for NANDing the burst mode control signal from said input terminal and a pulse signal at said third node; a sixth inverter for inverting an output signal from said third NAND gate; first PMOS and NMOS transistors connected in parallel between an output terminal of said second inverter and said multiplexing means; second PMOS and NMOS transistors connected in parallel between an output terminal of said fourth inverter and a fourth node; a NOR gate for NORing an output signal from said sixth inverter and a signal at said fourth node; and a seventh inverter for inverting an output signal from said NOR gate and outputting the inverted signal to said multiplexing means.

Claim 11

A signal transfer circuit for a synchronous memory device, as set forth in claim 1, wherein said switching means includes a transfer transistor circuit, said transfer transistor circuit having a PMOS transistor and an NMOS transistor connected in parallel between said internal circuit and said data output buffer means.

Claim 12

A signal transfer circuit for a synchronous memory device, as set forth in claim 10, wherein said switching means further includes a latch circuit connected to an output terminal of said transfer transistor circuit, for maintaining the data signal from said internal circuit.

Claim 13

A signal transfer circuit for a synchronous memory device, as set forth in claim 4, wherein said switching control means includes: a first edge detector for generating a first pulse signal when the delayed clock signal from said clock signal delay means makes a first to second state transition; a second edge detector for generating a second pulse signal when the delayed clock signal from said clock signal delay means makes the first to second state transition; and a latch circuit for latching the first and second pulse signals from said first and second edge detectors and outputting the latched result as a switching control signal to said switching means.

Claim 14

A signal transfer circuit for a synchronous memory device, as set forth in claim 12, wherein each of said first and second edge detectors includes a delay chain and a logic gate for cooperating to delay the delayed clock signal from said clock signal delay means for a predetermined time period to generate the first or second pulse signal.

Claim 15

A signal transfer circuit for a synchronous memory device, as set forth in claim 4, wherein said switching control means includes: a first edge detector for generating a first pulse signal when the delayed clock signal from said clock signal delay means makes a first to second state transition; and a second edge detector for generating a second pulse signal in response to the first pulse signal from said first edge detector and a delayed one of the first pulse signal from said first edge detector and outputting the generated second pulse signal as a switching control signal to said switching means.

Claim 16

A signal transfer circuit for a synchronous memory device, as set forth in claim 14, wherein said first edge detector includes a delay chain and a logic gate for cooperating to delay the delayed clock signal from said clock signal delay means for a predetermined time period to generate the first pulse signal.

Claim 17

A signal transfer circuit for a synchronous memory device, as set forth in claim 14, wherein said second edge detector includes a delay chain and a logic gate for cooperating to delay the first pulse signal from said first edge detector for a predetermined time period to generate the second pulse signal.

Claim 18

A signal transfer circuit for a synchronous memory device , as set forth in claim 4, wherein said switching control means includes: a first edge detector for generating a first pulse signal when the delayed clock signal from said clock signal delay means makes a first to second state transition; and a second edge detector for generating a second pulse signal in response to the first pulse signal from said first edge detector, to a delayed one of the first pulse signal from said first edge detector and to a signal obtained by NANDing an inverted one of the delayed first pulse signal and an inverted burst mode control signal, and for outputting the generated second pulse signal as a switching control signal to said switching means.

Claim 19

A signal transfer circuit for a synchronous memory device, as set forth in claim 17, wherein said first edge detector includes a delay chain and a logic gate for cooperating to delay the delayed clock signal from said clock signal delay means for a predetermined time period to generate the first pulse signal.