US5644533A
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Flash memory system, and methods of constructing and utilizing same
Assignee: RPX Corp
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Filing: 1993-11-02
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Granted: 1997-07-01
•
Expires: 2013-11-02
Abstract
Abstract PCT No. PCT/US93/10485 Sec. 371 Date Apr. 26, 1995 Sec. 102(e) Date Apr. 26, 1995 PCT Filed Nov. 2, 1993 PCT Pub. No. WO04/10686 PCT Pub. Date May 11, 1994An N-channel SNOS or SONOS type memory array (100) has programmable states with a negative, depletion mode threshold lower in magnitude than the supply voltage VCC when erased and a positive threshold when programmed. During reading, the supply voltage VCC is applied to the drain (16), while a positive voltage VR less than VCC-Vds,sat is applied to the source (14), where Vds,sat is the saturation voltage of the device. A reference voltage may also be applied to the substrate (11) during a read operation. Selected devices have VR applied to the gate (12), while inhibited devices have ground or the substrate potential VSS applied to the gate (12).
Inventors
- 👤 Loren T. Lancaster
- 👤 Ryan T. Hirose
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:31
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/06; G11C16/26; H; H10; H10B; H10B41/00; H10B41/30; H10B43/00; H10B43/30; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/69; H10W; H10W10/00; H10W10/01; H10W10/051; H10W10/50
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
151 words
A non-volatile integrated memory circuit, comprising: a semiconductor substrate; a memory transistor formed in said substrate, said memory transistor having a source, a drain, a gate, and a dielectric memory material that has programmable memory states that produce a first transistor threshold of magnitude less thin a magnitude of a supply voltage, V cc , when the memory transistor is erased and a different threshold when the memory transistor is programmed; biasing circuitry for applying selected read biasing voltages to the gate, drain, and source of said transistor, said read biasing voltages including a read voltage, V r , of magnitude less than the magnitude of the supply voltage applied to the source and gate, with the supply voltage applied between the drain the substrate; and sensing circuitry for sensing a current generated at the drain of said memory transistor in accordance with the programmable state of said dielectric memory material.
Claim 2
Dependent Claim
151 words
A non-volatile integrated memory circuit, comprising: a semiconductor substrate; a memory transistor formed in said substrate, said memory transistor having a source, a drain, a gate, and a dielectric memory material that has programmable memory states that produce a first transistor threshold of magnitude less thin a magnitude of a supply voltage, V cc , when the memory transistor is erased and a different threshold when the memory transistor is programmed; biasing circuitry for applying selected read biasing voltages to the gate, drain, and source of said transistor, said read biasing voltages including a read voltage, V r , of magnitude less than the magnitude of the supply voltage applied to the source and gate, with the supply voltage applied between the drain the substrate; and sensing circuitry for sensing a current generated at the drain of said memory transistor in accordance with the programmable state of said dielectric memory material.
Claim 3
Dependent Claim
22 words
The non-volatile integrated memory circuit of claim 1 wherein said biasing circuitry further comprises circuitry for applying a voltage to the substrate.
Claim 4
Dependent Claim
44 words
The non-volatile integrated memory circuit of claim 2 wherein said memory transistor is an n-channel memory transistor, said supply voltage has a magnitude, V cc , applied to the drain, and said voltage applied to the substrate is a reference potential, v ss .
Claim 5
Dependent Claim
14 words
The non-volatile integrated memory circuit of claim 3 wherein said reference potential is ground.
Claim 6
Dependent Claim
18 words
The non-volatile integrated memory circuit of claim 3 wherein said reference potential is V r less than ground.
Claim 7
Dependent Claim
45 words
The non-volatile integrated memory circuit of claim 1 wherein said dielectric memory material is selected from the group comprising oxides, oxynitrides, ferroelectric materials, silicon rich oxide, silicon nitride, silicon oxy-nitride, silicon rich silicon dioxide, tantalum pentoxide, carbides, ceramics, aluminum oxide, silicon carbide and ferroelectric materials.
Claim 8
Dependent Claim
17 words
The non-volatile integrated memory circuit of claim 1 wherein said dielectric memory material is a multilayered dielectric.
Claim 9
Dependent Claim
14 words
The non-volatile integrated memory circuit of claim 7 wherein said multilayered dielectric is SNOS.
Claim 10
Dependent Claim
14 words
The non-volatile integrated memory circuit of claim 7 wherein said multilayered dielectric is SONOS.
Claim 11
Dependent Claim
46 words
The non-volatile integrated memory circuit of claim 1 wherein said memory transistor is an n-channel device, said supply voltage is applied to the drain, and said read voltage is of magnitude larger than a threshold voltage of the memory transistor after it has been freshly erased.
Claim 12
Dependent Claim
50 words
The non-volatile integrated memory circuit of claim 1 wherein a difference between a potential on the drain of said memory transistor and said read voltage is of magnitude greater than V cc -V ds ,sat, where V ds ,sat is the magnitude of the saturation voltage of the memory transistor.
Claim 13
Dependent Claim
160 words
A non-volatile integrated memory array, comprising: a semiconductor substrate; a plurality of addressable memory transistors in said substrate, each of said memory transistors having a source, a drain, a gate, and a dielectric memory material that has programmable memory states that produce a first threshold of magnitude less than a magnitude of a supply voltage when the memory transistor is erased and a different threshold when the memory transistor is programmed; biasing circuitry for applying selected read biasing voltages to the gate, drain, and source of at least an addressed one of said memory transistors, said read biasing voltages including a read voltage, V r , of magnitude less than the supply voltage, applied to the source and gate, with the supply voltage applied between the drain and substrate; and sensing circuitry for sensing a current generated at the drain of said memory transistor in accordance with the programmable state of said dielectric memory material of said addressed memory transistor.
Claim 14
Dependent Claim
160 words
A non-volatile integrated memory array, comprising: a semiconductor substrate; a plurality of addressable memory transistors in said substrate, each of said memory transistors having a source, a drain, a gate, and a dielectric memory material that has programmable memory states that produce a first threshold of magnitude less than a magnitude of a supply voltage when the memory transistor is erased and a different threshold when the memory transistor is programmed; biasing circuitry for applying selected read biasing voltages to the gate, drain, and source of at least an addressed one of said memory transistors, said read biasing voltages including a read voltage, V r , of magnitude less than the supply voltage, applied to the source and gate, with the supply voltage applied between the drain and substrate; and sensing circuitry for sensing a current generated at the drain of said memory transistor in accordance with the programmable state of said dielectric memory material of said addressed memory transistor.
Claim 15
Dependent Claim
16 words
The non-volatile integrated memory array of claim 12 further comprising circuitry for deselecting nonaddressed memory transistors.
Claim 16
Dependent Claim
22 words
The non-volatile integrated memory circuit of claim 13 wherein said biasing circuitry further comprises circuitry for applying a voltage to the substrate.
Claim 17
Dependent Claim
44 words
The non-volatile integrated memory circuit of claim 14 wherein said memory transistors are an n-channel memory transistors, said supply voltage is applied to the drains of the n-channel memory transistors, and said voltage applied to the substrate is a reference potential, V ss .
Claim 18
Dependent Claim
18 words
The non-volatile integrated memory circuit of claim 15 wherein said reference potential is V r less than ground.
Claim 19
Dependent Claim
14 words
The non-volatile integrated memory circuit of claim 15 wherein said reference potential is ground.
Claim 20
Dependent Claim
83 words
The non-volatile integrated memory array of claim 13 wherein said nonaddressed memory transistors are n-channel devices and said circuitry for deselecting nonaddressed memory transistors comprises circuitry for applying selected inhibit biasing voltages to the gate, drain, and source of nonaddressed memory transistors, said inhibit biasing voltages including a supply voltage applied to the drains, and a read voltage, V r , of magnitude less than the supply voltage applied to the sources, and a reference potential, V ss , applied to the gates.
Claim 21
Dependent Claim
45 words
The non-volatile integrated memory circuit of claim 12 wherein said dielectric memory material is selected from the group comprising oxides, oxynitrides, ferroelectric materials, silicon rich oxide, silicon nitride, silicon oxy-nitride, silicon rich silicon dioxide, tantalum pentoxide, carbides, ceramics, aluminum oxide, silicon carbide and ferroelectric materials.
Claim 22
Dependent Claim
17 words
The non-volatile integrated memory circuit of claim 12 wherein said dielectric memory material is a multilayered dielectric.
Claim 23
Dependent Claim
14 words
The non-volatile integrated memory circuit of claim 20 wherein said multilayered dielectric is SNOS.
Claim 24
Dependent Claim
14 words
The non-volatile integrated memory circuit of claim 20 wherein said multilayered dielectric is SONOS.
Claim 25
Dependent Claim
37 words
The non-volatile integrated memory circuit of claim 12 wherein said memory transistors are n-channel devices and said read voltage is of magnitude larger than a threshold voltage of the memory transistor after it has been freshly erased.
Claim 26
Dependent Claim
51 words
The non-volatile integrated memory circuit of claim 12 wherein the potential difference between said voltage applied to the drain and said read voltage is of magnitude greater than the supply voltage minus V ds ,sat , where V ds ,sat is the magnitude of the saturation voltage of the memory transistor.
Claim 27
Independent Claim
132 words
A method for operating a non-volatile integrated memory circuit having at least one memory cell with a single memory transistor having a source, a drain, a gate, and a dielectric memory material that has programmable memory states that produce a first transistor threshold of magnitude less than a magnitude of a supply voltage, when the memory transistor is erased and a different threshold when the memory transistor is programmed, comprising: applying read biasing voltages to said memory transistor, including a read voltage, V r , of magnitude less than the magnitude of the supply voltage to the source and gate, with the supply voltage applied between the drain and substrate; and sensing a current generated at the drain of said memory transistor in accordance with a programmable state of dielectric memory material.
Claim 28
Independent Claim
132 words
A method for operating a non-volatile integrated memory circuit having at least one memory cell with a single memory transistor having a source, a drain, a gate, and a dielectric memory material that has programmable memory states that produce a first transistor threshold of magnitude less than a magnitude of a supply voltage, when the memory transistor is erased and a different threshold when the memory transistor is programmed, comprising: applying read biasing voltages to said memory transistor, including a read voltage, V r , of magnitude less than the magnitude of the supply voltage to the source and gate, with the supply voltage applied between the drain and substrate; and sensing a current generated at the drain of said memory transistor in accordance with a programmable state of dielectric memory material.
Claim 29
Dependent Claim
20 words
The method of claim 25 further comprising applying a further read biasing voltage by applying a voltage to the substrate.
Claim 30
Dependent Claim
43 words
The method of claim 26 wherein said memory transistor is an n-channel device and said step of applying read biasing voltages comprises applying said voltage to the substrate at a reference potential, V ss , and applying said supply voltage to the drain.
Claim 31
Dependent Claim
41 words
The method of claim 25 further comprising selecting said dielectric material from the group comprising oxides, oxynitrides, ferroelectric materials, silicon rich oxide, silicon nitride, silicon oxy-nitride, silicon rich silicon dioxide, tantalum pentoxide, carbides, ceramics, aluminum oxide, silicon carbide and ferroelectric materials.
Claim 32
Dependent Claim
16 words
The method of claim 25 further comprising forming said dielectric memory material from a multilayered dielectric.
Claim 33
Dependent Claim
14 words
The method of claim 25 further comprising forming said dielectric memory material from SNOS.
Claim 34
Dependent Claim
14 words
The method of claim 25 further comprising forming said dielectric memory material from SONOS.
Claim 35
Dependent Claim
57 words
The method of claim 25 wherein said memory transistor is an n-channel device and said applying read biasing voltages further comprises establishing said read voltage to have a magnitude larger than a threshold voltage of the memory transistor after it has been freshly erased, and applying said supply voltage applied to the drain of said n-channel device.
Claim 36
Dependent Claim
50 words
The method of claim 25 wherein said biasing further comprises establishing the potential difference between the drain voltage and said read voltage to have a magnitude larger than the supply voltage minus V ds ,sat, where V ds ,sat is the magnitude of a saturation voltage of the memory transistor.
Claim 37
Independent Claim
140 words
A method for reading an array of non-volatile integrated memory cells, each cell having a single memory transistor having a source, a drain, a gate, and a dielectric memory material that has programmable memory states that produce a first transistor threshold of magnitude less than a supply voltage when the memory transistor is erased and a different threshold when the memory transistor is programmed, comprising: applying read biasing voltages to a memory transistor of an addressed one of said cells, said read biasing voltages including a read voltage, V r , of magnitude less than the magnitude of the supply voltage to the source and gate and with the supply voltage applied between the drain and substrate; and sensing a current generated at the drain of said memory transistor in accordance with a programmable state of said dielectric memory material.
Claim 38
Independent Claim
140 words
A method for reading an array of non-volatile integrated memory cells, each cell having a single memory transistor having a source, a drain, a gate, and a dielectric memory material that has programmable memory states that produce a first transistor threshold of magnitude less than a supply voltage when the memory transistor is erased and a different threshold when the memory transistor is programmed, comprising: applying read biasing voltages to a memory transistor of an addressed one of said cells, said read biasing voltages including a read voltage, V r , of magnitude less than the magnitude of the supply voltage to the source and gate and with the supply voltage applied between the drain and substrate; and sensing a current generated at the drain of said memory transistor in accordance with a programmable state of said dielectric memory material.
Claim 39
Dependent Claim
13 words
The method of claim 34 further comprising deselecting memory transistors of nonaddressed cells.
Claim 40
Dependent Claim
87 words
The method of claim 35 wherein said deselected memory transistor is an n-channel device and said step of deselecting memory transistors of nonaddressed cells comprises applying selected inhibit biasing voltages to the gate, drain, and source of memory transistors of said nonaddressed cells, said inhibit biasing voltages including the supply voltage, V cc , applied to the drains, and a read voltage, V r , of magnitude less than the supply voltage, applied to the sources, and a reference potential, V ss , applied to the gates.
Claim 41
Dependent Claim
15 words
The method of claim 34 further comprising applying a read biasing voltage to the substrate.
Claim 42
Dependent Claim
50 words
The method of claim 37 wherein said memory transistors are n-channel devices and said step of applying a read biasing voltage to the substrate comprises applying a reference potential, V ss , to said substrate, and establishing said voltage applied to the drain at the supply voltage, V cc .
Claim 43
Dependent Claim
31 words
The method of claim 37 wherein said step of applying a read biasing voltage to the substrate comprises applying a reference potential of V r less than ground to said substrate.
Claim 44
Dependent Claim
42 words
The method of claim 34 further comprising selecting said dielectric memory material from the group comprising oxides, oxynitrides, ferroelectric materials, silicon rich oxide, silicon nitride, silicon oxy-nitride, silicon rich silicon dioxide, tantalum pentoxide, carbides, ceramics, aluminum oxide, silicon carbide and ferroelectric materials.
Claim 45
Dependent Claim
16 words
The method of claim 34 further comprising selecting said dielectric memory material is a multilayered dielectric.
Claim 46
Dependent Claim
21 words
The method of claim 41 wherein said step of selecting said dielectric memory material is a multilayered dielectric is selecting SNOS.
Claim 47
Dependent Claim
21 words
The method of claim 41 wherein said step of selecting said dielectric memory material is a multilayered dielectric is selecting SONOS.
Claim 48
Dependent Claim
54 words
The method of claim 34 wherein said memory transistors are n-channel devices and said biasing further comprises establishing said read voltage to have a magnitude larger than a threshold voltage of the memory transistor after it has been freshly erased, and said voltage applied to the drain at the supply voltage, V cc .
Claim 49
Dependent Claim
49 words
The method of claim 34 further establishing the potential difference between said voltage applied to the drain and said read voltage to have a magnitude greater than the supply voltage minus V ds ,sat, where V ds ,sat is the magnitude of a saturation voltage of the memory transistor.
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| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
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