Voltage booster circuit with plural booster units having outputs connected in common

Claim 2

A booster circuit having a first booster circuit section and a second booster circuit section which have the same structure, each of the first and second booster circuit sections comprising: a plurality of first MOS transistors, said first MOS transistors each having a gate terminal and two current terminals and connected to one another in series; a plurality of second MOS transistors, said second MOS transistors each having a gate terminal and two current terminals, first one of said current terminals of each second MOS transistor connected to one of the current terminals of the first MOS transistor, second one of said current terminals of each second MOS transistor connected to the gate of the first MOS transistor, said gate terminal, excluding a case of a gate terminal of a second MOS transistor in a final stage, connected to the second one of the current terminals of the first MOS transistor, said gate terminal of the second MOS transistor in a final stage connected to a final node between first MOS transistors of another booster circuit section; a plurality of first capacitors each having one terminal connected to the gate of each first MOS transistor; and a plurality of second capacitors each having one terminal connected to a node between said first MOS transistors, wherein clock pulses are inputted to second terminals of said first and second capacitors, the second terminals of the first and second capacitors of the first booster circuit section and the second terminals of the first and second capacitors of the second booster circuit section being terminals which correspond to each other and which are supplied with clock pulses opposite each other in phase.

Claim 3

A booster circuit having a first booster circuit section and a second booster circuit section which have the same structure, each of the first and second booster circuit sections comprising: a first group of transistors including a plurality of first MOS transistors, said first MOS transistors each having a gate terminal and two current terminals and connected to one another in series; a second group of transistors including a plurality of second MOS transistors which are the same in number as the first group of MOS transistors, said second MOS transistors each having a gate terminal and two current terminals, first one of said current terminals of each second MOS transistor connected to one of the current terminals of the first MOS transistor, second one of said current terminals of said second MOS transistor connected to the gate of the first MOS transistor, said gate terminal, excluding a case of a gate terminal of a second MOS transistor in a final stage, connected to the second one of the current terminals of the first MOS transistor, said gate terminal of the second MOS transistor in a final stage connected to a final node between first MOS transistors of another booster circuit section; a first group of capacitors including first capacitors, which are the same in number as the first MOS transistors, said first capacitors each having oneterminal connected to the gate of each first MOS transistor; and a second group of capacitors including second capacitors each having one terminal connected to a node between said first MOS transistors, wherein clock pulses are inputted to second terminals of said first and second capacitors, the second terminals of the first and second capacitors of the first booster circuit section and the second terminals of the first and second capacitors of the second booster circuit section being terminals which correspond to each other and which are supplied with clock pulses opposite each other in phase.

Claim 4

A booster circuit having a first booster circuit section and a second booster circuit section which have the same structure, each of the first and second booster circuit sections comprising: a first group of transistors including a plurality of first MOS transistors, said first MOS transistors each having a gate terminal and two current terminals and connected to one another in series; a second group of transistors including a plurality of second MOS transistors which are the same in number as the first group of MOS transistors, said second MOS transistors each having a gate terminal and two current terminals, first one of said current terminals of each second MOS transistor connected to one of the current terminals of the first MOS transistor, second one of said current terminals of said second MOS transistor connected to the gate of the first MOS transistor, said gate terminal, excluding a case of a gate terminal of a second MOS transistor in a final stage, connected to the second one of the current terminals of the first MOS transistor, said gate terminal of the second MOS transistor in a final stage connected to a final node between first MOS transistors of another booster circuit section; a first group of capacitors including first capacitors, which are the same in number as the first MOS transistors, said first capacitors each having oneterminal connected to the gate of each first MOS transistor; and a second group of capacitors including second capacitors each having one terminal connected to a node between said first MOS transistors, wherein clock pulses are inputted to second terminals of said first and second capacitors, the second terminals of the first and second capacitors of the first booster circuit section and the second terminals of the first and second capacitors of the second booster circuit section being terminals which correspond to each other and which are supplied with clock pulses opposite each other in phase.

Claim 5

A booster circuit comprising: (a) first and second circuit sections each having a voltage input section and a voltage output section, the first and second circuit sections each comprising: a booster block having a plurality of booster units each having an input terminal, an output terminal and a control input, the booster units being arranged in series between the voltage input section and the voltage output section by connecting the input terminal and the output terminal between adjacent booster units; and an output switch block arranged between and output terminal of a final-stage booster unit of said booster block, and the voltage output section; and (b) a voltage output node for connecting the voltage output sections of said first and second circuit sections in common each other, wherein the output switch block comprises: (i) a first transistor having two current terminals connected to the output terminal of the final-stage booster unit and to the voltage output section, respectively, and a gate terminal; (ii) a second transistor having two current terminals connected to the gate terminal of said first transistor and to the output terminal of the final-stage booster unit, respectively, and a gate terminal; and (iii) a first capacitor having a first terminal connected to the gate terminal of the first transistor, and a second terminal serving as an input terminal of a clock pulse, and wherein clock pulses inputted to the first and second output switch blocks of the first and second circuit sections have phases opposite each other, and a gate electrode of the second transistor of one of the output switch blocks is connected to the output terminal of the final-stage booster unit of the other output switch block.

Claim 6

A booster circuit comprising: (a) first and second circuit sections each having a voltage input section and a voltage output section, the first and second circuit sections each comprising: a booster block having a plurality of booster units each having an input terminal, an output terminal and a control input, the booster units being arranged in series between the voltage input section and the voltage output section by connecting the input terminal and the output terminal between adjacent booster units; and an output switch block arranged between and output terminal of a final-stage booster unit of said booster block, and the voltage output section; and (b) a voltage output node for connecting the voltage output sections of said first and second circuit sections in common each other, wherein the output switch block comprises: (i) a first transistor having two current terminals connected to the output terminal of the final-stage booster unit and to the voltage output section, respectively, and a gate terminal; (ii) a second transistor having two current terminals connected to the gate terminal of said first transistor and to the output terminal of the final-stage booster unit, respectively, and a gate terminal; and (iii) a first capacitor having a first terminal connected to the gate terminal of the first transistor, and a second terminal serving as an input terminal of a clock pulse, and wherein clock pulses inputted to the first and second output switch blocks of the first and second circuit sections have phases opposite each other, and a gate electrode of the second transistor of one of the output switch blocks is connected to the output terminal of the final-stage booster unit of the other output switch block.

Claim 7

A booster circuit according to claim 3, wherein the first and second circuit sections comprise an equal number of booster units, and the clock pulses having phases opposite each other are respectively inputted to the control inputs of the corresponding booster units between the first and second circuit sections.

Claim 8

A booster circuit according to claim 3, wherein each of the booster units comprise: a third transistor having two current terminals connected to the input terminal and the output terminal, respectively, and a gate terminal; a fourth transistor having two current terminals connected to the gate terminal of said third transistor and the input terminal, respectively, and a gate terminal connected to the output terminal; a second capacitor having a first terminal connected to the gate terminal of the third transistor and a second terminal serving as an input terminal of a first clock pulse; and a third capacitor having a first terminal connected to the gate terminal of the fourth transistor and a second terminal serving as an input terminal of a second clock pulse.

Claim 9

A booster circuit according to claim 5, wherein the third and fourth transistors are MOS transistors selected from a group consisting of an N-MOSFET and a P-MOSFET.

Claim 10

A booster circuit according to claim 3, wherein the first and second transistors are MOS transistors selected from a group consisting of an N-MOSFET and a P-MOSFET.

Claim 11

A booster circuit according to claim 5, wherein the clock pulse inputted to each of the output switch blocks is the first clock pulse.