Patent US5646828A successfully refreshed from Google Patents.
US5646828A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Thin packaging of multi-chip modules with enhanced thermal/power management
Assignee: Bell Semiconductor LLC
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Filing: 1996-08-20
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Granted: 1997-07-08
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Expires: 2016-08-20
Abstract
Abstract A novel packaging of semiconductor elements, such as MCM tiles, with a variety of printed circuit or wired boards (PWB), the packages occupying a small size, at least in the vertical direction, relative to prior art OMPAC devices. The MCM tile includes an interconnection substrate with peripheral metallizations and at least one chip or integrated circuit (IC) mounted on the substrate by solder reflow or conductive adhesive technology. The PWB which may be a single level or a multilevel, is provided with an aperture for accommodation of at least one chip therein. Depending on the type of interconnection between the substrate and the PWB, the aperture may be larger than the substrate of the MCM tile for wire bonding interconnection or smaller than the substrate for solder reflow or conductive adhesive interconnection. In the wire bonding case, the MCM tile is positioned within the aperture resting on the surface of the PWB or of a structural member or of a heat sink which encloses one end of the aperture. The other end of the aperture may be open or enclosed by a structural member, a heat sink, another PWB or a mother board. For solder reflow or conductive adhesive interconnection, the substrate which is larger than the aperture is positioned so that its ends overlap areas of the PWB adjacent the aperture and the chips and/or substrate are positioned within the aperture. The interconnections are enclosed in a compliable encapsulating material, such as silica gel.
Inventors
- 👤 Yinon Degani
- 👤 Thomas Dixon Dudderar
- 👤 Byung Joon Han
- 👤 Alan Michael Lyons
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:00
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/20; H10W40/22; H10W40/226; H10W40/228; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/69; H10W70/698; H10W76/00; H10W76/40; H10W76/42; H10W76/47; H10W90/00; H10W90/401; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/141; H05K1/142; H05K1/18; H05K1/182; H10W70/681; H10W70/682; H10W70/685; H10W72/00; H10W72/851; H10W72/874; H10W72/877; H10W74/00; H10W74/10; H10W74/131; H10W74/142; H10W90/701; H10W90/721; H10W90/722; H10W90/724; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
304 words
A multi-chip module (MCM) package comprising: a. a first printed wiring board (PWB) provided with at least one aperture extending from the top surface of said first PWB through the thickness of said first PWB to the bottom surface of said first PWB, b. a structural member attached to the bottom surface of said first PWB and covering said at least one aperture, c. a pattern of electrical conductors on the top surface of said first PWB, d. a multi-chip module tile positioned within said aperture with part of the multi-chip module tile contained within the aperture and part of the multi-chip module tile extending above the top surface of the first PWB, said multi-chip module further being attached to said structural member, said multi-chip module tile comprising a substrate with electrical conductors thereon, at least one silicon chip mounted on the substrate and electrically interconnected to electrical conductors on the substrate, with electrical conductors on the substrate interconnected to said pattern of electrical conductors on said first PWB, e. a plurality of solder or conductive adhesive bonding means on the top surface of said first PWB, said bonding means interconnected to said pattern of electrical conductors on the top surface of the said first PWB, f. a second PWB having at least one aperture extending from the top surface of said second PWB through the thickness of said second PWB to the bottom surface of said second PWB, said second PWB being bonded to said first PWB by said bonding means, and positioned so that the portion of said multi-chip module tile fits at least partially within the aperture in the second PWB, g. encapsulation means comprising an encapsulating material encompassing the multi-chip module tile, and the electrical conductors interconnecting the silicon chip to the substrate and the substrate to the first PWB.
Claim 2
Dependent Claim
304 words
A multi-chip module (MCM) package comprising: a. a first printed wiring board (PWB) provided with at least one aperture extending from the top surface of said first PWB through the thickness of said first PWB to the bottom surface of said first PWB, b. a structural member attached to the bottom surface of said first PWB and covering said at least one aperture, c. a pattern of electrical conductors on the top surface of said first PWB, d. a multi-chip module tile positioned within said aperture with part of the multi-chip module tile contained within the aperture and part of the multi-chip module tile extending above the top surface of the first PWB, said multi-chip module further being attached to said structural member, said multi-chip module tile comprising a substrate with electrical conductors thereon, at least one silicon chip mounted on the substrate and electrically interconnected to electrical conductors on the substrate, with electrical conductors on the substrate interconnected to said pattern of electrical conductors on said first PWB, e. a plurality of solder or conductive adhesive bonding means on the top surface of said first PWB, said bonding means interconnected to said pattern of electrical conductors on the top surface of the said first PWB, f. a second PWB having at least one aperture extending from the top surface of said second PWB through the thickness of said second PWB to the bottom surface of said second PWB, said second PWB being bonded to said first PWB by said bonding means, and positioned so that the portion of said multi-chip module tile fits at least partially within the aperture in the second PWB, g. encapsulation means comprising an encapsulating material encompassing the multi-chip module tile, and the electrical conductors interconnecting the silicon chip to the substrate and the substrate to the first PWB.
Claim 3
Dependent Claim
102 words
The MCM package of claim 1, in which said first PWB is a single level PWB, the aperture extends through the PWB a dam is on an upper surface of said first PWB, the dam is spaced a distance from an edge of the aperture sufficiently to permit a wirebond connection between the circuitry on the silicon substrate of the MCM tile and the circuitry on said first PWB, and said at least one chip is within a cavity formed by the structural member, walls of the aperture in said first PWB and the dam, said structural member being a heat sink.
Claim 4
Dependent Claim
12 words
The MCM package of claim 1, in which said substrate comprises silicon.
Claim 5
Dependent Claim
20 words
The MCM package of claim 1, in which said at least one silicon chip is flip-chip mounted on the substrate.
Claim 6
Dependent Claim
25 words
The MCM package of claim 1, in which said structural member is of a heat conducting material, and provides a heat sink for the substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |