Patent US5648276A successfully refreshed from Google Patents.
US5648276A
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Method and apparatus for fabricating a thin film semiconductor device
Assignee: Sony Corp
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Filing: 1994-05-26
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Granted: 1997-07-15
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Expires: 2014-05-26
Abstract
Abstract A method and an apparatus for fabricating a thin film semiconductor device are disclosed. An a-Si:H thin film produced on a wafer is melting-recrystallized by irradiating a laser beam to it in a laser annealing chamber to produce a polycrystalline Si thin film. The wafer is then transported to a CVD chamber without exposing it to the outside air. A gate insulating film is produced on a clean surface of the polycrystalline Si thin film in the CVD chamber. In another case, an a-Si:H thin film is melting-recrystallized in the laser annealing chamber to produce a polycrystalline Si thin film and then the wafer is transported to a hydrogenating chamber without exposing it to the outside air. Thereafter the polycrystalline Si thin film is plasma hydrogenated in the hydrogenating chamber. The method and apparatus can fabricate thin film semiconductor devices having a high performance and a high reliability with a good uniformity by making a clean and high quality semiconductor/insulator interface or by hydrogenating a semiconductor thin film without changes in electrical conductivity.
Inventors
- 👤 Masaki Hara
- 👤 Naoki Sano
- 👤 Toshiyuki Sameshima
- 👤 Atsushi Kohno
- 👤 Mitsunobu Sekiya
- 👤 Yasuhiro Kanaya
- 👤 Michihisa Yano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:52
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/04; H10P72/0451; H10P72/0468; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/673; H10D30/6731; H10D30/6737; H10D30/6739; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6757
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
191 words
A method for making a thin film semiconductor device, comprising the steps of: (a) providing a substrate having a surface; depositing an a-Si:H,P layer on said surface by plasma CVD; (c) patterning and etching the a-Si:H,P layer to define a channel region; (d) depositing an a-Si:H layer thereon; (e) laser annealing to convert the a-Si:H,P and a-Si:H layers into a first polycrystalline Si layer having defined n + -type source and drain regions and having a first crystal grain size; (f) depositing a second a-Si:H layer on said first polycrystalline Si layer; (g) laser annealing to convert the second a-Si:H and first polycrystalline Si layers into a second polycrystalline Si film having a second crystal grain size larger than said first crystal grain size; (h) depositing a gate insulating layer thereon; (i) patterning and etching to form islands; (j) etching the gate insulating layer to define contact holes; (k) depositing an electrode layer thereon; and (l) patterning and etching said electrode layer to define a source electrode, a drain electrode and a gate electrode, wherein each of steps (a)-(l) are performed in a multi-chambered apparatus, without being exposed to outside air.
Claim 2
Independent Claim
191 words
A method for making a thin film semiconductor device, comprising the steps of: (a) providing a substrate having a surface; depositing an a-Si:H,P layer on said surface by plasma CVD; (c) patterning and etching the a-Si:H,P layer to define a channel region; (d) depositing an a-Si:H layer thereon; (e) laser annealing to convert the a-Si:H,P and a-Si:H layers into a first polycrystalline Si layer having defined n + -type source and drain regions and having a first crystal grain size; (f) depositing a second a-Si:H layer on said first polycrystalline Si layer; (g) laser annealing to convert the second a-Si:H and first polycrystalline Si layers into a second polycrystalline Si film having a second crystal grain size larger than said first crystal grain size; (h) depositing a gate insulating layer thereon; (i) patterning and etching to form islands; (j) etching the gate insulating layer to define contact holes; (k) depositing an electrode layer thereon; and (l) patterning and etching said electrode layer to define a source electrode, a drain electrode and a gate electrode, wherein each of steps (a)-(l) are performed in a multi-chambered apparatus, without being exposed to outside air.
Claim 3
Dependent Claim
39 words
A method as defined in claim 1, wherein steps (f) and (g) are repeated in order a plurality of times until a polycrystalline Si film layer of increased crystal grain size is obtained and thereafter, proceeding with step h).
Claim 4
Independent Claim
203 words
A method for making a thin film semiconductor device, comprising the steps of: (a) providing a substrate having a surface; (b) depositing an a-Si:H,P layer on said surface by plasma CVD; (c) patterning and etching the a-Si:H, P layer to define a channel region; (d) depositing an a-Si:H layer thereon; (e) laser annealing to convert the a-Si:H,P and a-Si:H layers into a polycrystalline Si film having defined n + -type source and drain regions; (f) depositing a gate insulating layer thereon; (g) patterning and etching to form islands; (h) etching the gate insulating layer to define contact holes; (i) depositing an electrode layer thereon; and (j) patterning and etching said electrode layer to define a source electrode, a drain electrode and a gate electrode, (k) depositing an interlayer insulating film on said etched electrode layer; (l) patterning and etching said interlayer insulating film to form contact holes aligned with said source, drain and gate electrodes; (m) depositing a second electrode layer thereon; and (n) patterning and etching said second electrode layer to define an extended source electrode, an extended drain electrode and an extended gate electrode wherein each of steps (a)-(n) are performed in a multi-chambered apparatus, without being exposed to outside air.
Claim 5
Independent Claim
203 words
A method for making a thin film semiconductor device, comprising the steps of: (a) providing a substrate having a surface; (b) depositing an a-Si:H,P layer on said surface by plasma CVD; (c) patterning and etching the a-Si:H, P layer to define a channel region; (d) depositing an a-Si:H layer thereon; (e) laser annealing to convert the a-Si:H,P and a-Si:H layers into a polycrystalline Si film having defined n + -type source and drain regions; (f) depositing a gate insulating layer thereon; (g) patterning and etching to form islands; (h) etching the gate insulating layer to define contact holes; (i) depositing an electrode layer thereon; and (j) patterning and etching said electrode layer to define a source electrode, a drain electrode and a gate electrode, (k) depositing an interlayer insulating film on said etched electrode layer; (l) patterning and etching said interlayer insulating film to form contact holes aligned with said source, drain and gate electrodes; (m) depositing a second electrode layer thereon; and (n) patterning and etching said second electrode layer to define an extended source electrode, an extended drain electrode and an extended gate electrode wherein each of steps (a)-(n) are performed in a multi-chambered apparatus, without being exposed to outside air.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-14 | 2001-01-13 | 2001-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-14 | 2005-01-13 | 2005-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-14 | 2009-01-13 | 2009-07-15 | $7700.00 | Window Closed / Lapsed |