Guided transfers with variable stepping

Claim 2

A data processing device comprising: an internal memory storing data at a plurality of corresponding addresses, said plurality of addresses of said internal memory including a subset of internal addresses less than all possible addresses; an external memory interface operative to access an external memory having addresses not within said subset of internal addresses, wherein said internal memory and external memory comprise a single address space; packet transfer parameters stored at a predetermined set of addresses in said internal memory, said packet transfer parameters including an indication of a number of guide table entries and an initial table pointer indicating an address in said internal memory; a control circuit operative to receive a packet transfer request and connected to said internal memory to receive packet transfer parameters; a guide table including said number of guide table entries indicated in said packet transfer parameters, each guide table entry stored in said internal memory beginning at an initial address and including a start address, an address value and dimension values defining a block of addresses, each guide table entry including a table pointer indicating an initial address of a next guide table entry, a first guide table entry having an initial address corresponding to said table pointer of said packet transfer parameters; and an address generating circuit coupled to said control circuit, said internal memory and said external memory interface, said address generating circuit operative to receive said number of guide table entries and said table pointer from said packet transfer parameters, said address generating circuit forming a set of block of addresses for memory access corresponding said guide table entry by forming a block start address from a predetermined combination of said start address and said address value of said guide table entry pointed to by said table pointer, said first block start address being said start address, forming a block of addresses from said block start address and said dimension values of said guide table entry pointed to by said table pointer, performing a memory access at said block of addresses, and replacing said table pointer with said table pointer of said current guide table entry to point to a next entry in said guide table following said memory access if less memory accesses than said number of guide table entries have been performed; said address generating circuit generating addresses within both said subset of internal addresses of said internal memory and not within said subset of internal addresses corresponding to external memory, said address generating circuit accessing said external memory via said external memory interface.

Claim 3

The data processing device of claim 1, wherein: said address generating circuit forms said predetermined combination of said starting address and said address value of said guide table entry pointed to by said table pointer by adding said address value to said prior block starting address.

Claim 4

The data processing device of claim 1, wherein: said address generating circuit forms said predetermined combination of said starting address and said address value of said guide table entry pointed to by said table pointer by adding said guide table value pointed to by said table pointer to said starting address.

Claim 5

The data processing device of claim 1, wherein: said dimension values of each guide table entry comprise a horizontal dimension value and a vertical dimension value of an array of pixels.

Claim 6

The data processing device of claim 1, wherein: said memory access consists of a memory read from said block of addresses.

Claim 7

The data processing device of claim 1, wherein: said memory access consists of a memory write to said block of addresses.

Claim 8

An integrated circuit comprising on a single semiconductor chip: an internal memory storing data at a plurality of corresponding addresses, said plurality of addresses including a subset of internal addresses less than all possible addresses; an external memory interface operative to access external memory not included on said single semiconductor chip having addresses not within said subset of internal addresses, wherein said internal memory and external memory comprise a single address space; packet transfer parameters stored at a predetermined set of addresses in said internal memory, said packet transfer parameters including an indication of a number of guide table entries and an initial table pointer indicating an address in said internal memory; a guide table including said number of guide table entries indicated in said packet transfer parameters, each guide table entry stored in said internal memory beginning at an initial address and including a start address, an address value and dimension values defining a block of addresses, each guide table entry including a table pointer indicating an initial address of a next guide table entry, a first guide table entry having an initial address corresponding to said table pointer of said packet transfer parameters; a data processor having circuitry for generating packet transfer requests; a data transfer controller connected to said internal memory, said external memory interface and said data processor, said data transfer controller including a control circuit operative to receive a packet transfer request and initiate a packet transfer; and an address generating circuit coupled to said control circuit, said internal memory and said external memory interface, said address generating circuit operative to receive said number of guide table entries and said table pointer from said packet transfer parameters, said address generating circuit forming a set of block of addresses for memory access corresponding said guide table entry by forming a block start address from a predetermined combination of said start address and said address value of said guide table entry pointed to by said table pointer, said first block start address being said start address, forming a block of addresses from said block start address and said dimension values of said guide table entry pointed to by said table pointer, performing a memory access at said block of addresses, and replacing said table pointer with said table pointer of said current guide table entry to point to a next entry in said guide table following said memory access if less memory accesses than said number of guide table entries have been performed; said address generating circuit generating addresses within both said subset of internal addresses of said memory and not within said subset of internal addresses corresponding to external memory, said address generating circuit accessing said external memory via said external memory interface.

Claim 9

An integrated circuit comprising on a single semiconductor chip: an internal memory storing data at a plurality of corresponding addresses, said plurality of addresses including a subset of internal addresses less than all possible addresses; an external memory interface operative to access external memory not included on said single semiconductor chip having addresses not within said subset of internal addresses, wherein said internal memory and external memory comprise a single address space; packet transfer parameters stored at a predetermined set of addresses in said internal memory, said packet transfer parameters including an indication of a number of guide table entries and an initial table pointer indicating an address in said internal memory; a guide table including said number of guide table entries indicated in said packet transfer parameters, each guide table entry stored in said internal memory beginning at an initial address and including a start address, an address value and dimension values defining a block of addresses, each guide table entry including a table pointer indicating an initial address of a next guide table entry, a first guide table entry having an initial address corresponding to said table pointer of said packet transfer parameters; a data processor having circuitry for generating packet transfer requests; a data transfer controller connected to said internal memory, said external memory interface and said data processor, said data transfer controller including a control circuit operative to receive a packet transfer request and initiate a packet transfer; and an address generating circuit coupled to said control circuit, said internal memory and said external memory interface, said address generating circuit operative to receive said number of guide table entries and said table pointer from said packet transfer parameters, said address generating circuit forming a set of block of addresses for memory access corresponding said guide table entry by forming a block start address from a predetermined combination of said start address and said address value of said guide table entry pointed to by said table pointer, said first block start address being said start address, forming a block of addresses from said block start address and said dimension values of said guide table entry pointed to by said table pointer, performing a memory access at said block of addresses, and replacing said table pointer with said table pointer of said current guide table entry to point to a next entry in said guide table following said memory access if less memory accesses than said number of guide table entries have been performed; said address generating circuit generating addresses within both said subset of internal addresses of said memory and not within said subset of internal addresses corresponding to external memory, said address generating circuit accessing said external memory via said external memory interface.

Claim 10

The integrated circuit of claim 7, wherein: said address generating circuit forms said predetermined combination of said starting address and said address value of said guide table entry pointed to by said table pointer by adding said address value to said prior block starting address.

Claim 11

The integrated circuit of claim 7, wherein: said address generating circuit forms said predetermined combination of said starting address and said address value of said guide table entry pointed to by said table pointer by adding said guide table value pointed to by said table pointer to said starting address.

Claim 12

The integrated circuit of claim 7, wherein: said dimension values of each guide table entry comprise a horizontal dimension value and a vertical dimension value of an array of pixels.

Claim 13

The integrated circuit of claim 7, wherein: said memory access consists of a memory read from said block of addresses.

Claim 14

The integrated circuit of claim 7, wherein: said memory access consists of a memory write to said block of addresses.

Claim 15

A data processing device comprising: an internal memory storing data at a plurality of corresponding addresses, said plurality of addresses of said internal memory including a subset of internal addresses less than all possible addresses; an external memory interface operative to access an external memory having addresses not within said subset of internal addresses, wherein said internal memory and external memory comprise a single address space; packet transfer parameters stored at a predetermined set of addresses in said internal memory, said packet transfer parameters including an indication of a number of guide table entries and an initial table pointer indicating an address in said internal memory; a guide table including said number of guide table entries indicated in said packet transfer parameters, each guide table entry stored in said internal memory beginning at an initial address and including a source start address, a source address value and source dimension values defining a source block of addresses and a destination start address, a destination address value and destination dimension values defining a destination block of addresses, each guide table entry including a table pointer indicating an initial address of a next guide table entry, a first guide table entry having an initial address corresponding to said table pointer of said packet transfer parameters; and an address generating circuit coupled to said control circuit and to said internal memory, said address generating circuit operative to receive said number of guide table entries and said table pointer from said packet transfer parameters, said address generating circuit forming a set of source and destination block of addresses for memory access corresponding said guide table entry by forming a source block start address from a predetermined combination of said source start address and said source address value of said guide table entry pointed to by said table pointer, said first source block start address being said start address, forming a block of source addresses from said source block start address and said source dimension values of said guide table entry pointed to by said table pointer, forming a destination block start address from a predetermined combination of said destination start address and said destination address value of said guide table entry pointed to by said table pointer, said first destination block start address being said start address, forming a block of destination addresses from said destination block start address and said destination dimension values of said guide table entry pointed to by said table pointer, performing a memory transfer of data from said block of source addresses to said block of destination addresses, and replacing said table pointer with said table pointer of said current guide table entry to point to a next entry in said guide table following said memory access if less memory accesses than said number of guide table entries have been performed; said address generating circuit generating addresses within both said subset of internal addresses of said internal memory and not within said subset of internal addresses corresponding to external memory, said address generating circuit accessing said external memory via said external memory interface.

Claim 16

A data processing device comprising: an internal memory storing data at a plurality of corresponding addresses, said plurality of addresses of said internal memory including a subset of internal addresses less than all possible addresses; an external memory interface operative to access an external memory having addresses not within said subset of internal addresses, wherein said internal memory and external memory comprise a single address space; packet transfer parameters stored at a predetermined set of addresses in said internal memory, said packet transfer parameters including an indication of a number of guide table entries and an initial table pointer indicating an address in said internal memory; a guide table including said number of guide table entries indicated in said packet transfer parameters, each guide table entry stored in said internal memory beginning at an initial address and including a source start address, a source address value and source dimension values defining a source block of addresses and a destination start address, a destination address value and destination dimension values defining a destination block of addresses, each guide table entry including a table pointer indicating an initial address of a next guide table entry, a first guide table entry having an initial address corresponding to said table pointer of said packet transfer parameters; and an address generating circuit coupled to said control circuit and to said internal memory, said address generating circuit operative to receive said number of guide table entries and said table pointer from said packet transfer parameters, said address generating circuit forming a set of source and destination block of addresses for memory access corresponding said guide table entry by forming a source block start address from a predetermined combination of said source start address and said source address value of said guide table entry pointed to by said table pointer, said first source block start address being said start address, forming a block of source addresses from said source block start address and said source dimension values of said guide table entry pointed to by said table pointer, forming a destination block start address from a predetermined combination of said destination start address and said destination address value of said guide table entry pointed to by said table pointer, said first destination block start address being said start address, forming a block of destination addresses from said destination block start address and said destination dimension values of said guide table entry pointed to by said table pointer, performing a memory transfer of data from said block of source addresses to said block of destination addresses, and replacing said table pointer with said table pointer of said current guide table entry to point to a next entry in said guide table following said memory access if less memory accesses than said number of guide table entries have been performed; said address generating circuit generating addresses within both said subset of internal addresses of said internal memory and not within said subset of internal addresses corresponding to external memory, said address generating circuit accessing said external memory via said external memory interface.

Claim 17

The data processing device of claim 13, wherein: said address generating circuit forms said predetermined combination of said source starting address and said source address value of said guide table entry pointed to by said table pointer by adding said source address value to said prior source block starting address.

Claim 18

The data processing device of claim 13, wherein: said address generating circuit forms said predetermined combination of said destination starting address and said destination address value of said guide table entry pointed to by said table pointer by adding said destination address value to said prior destination block starting address.

Claim 19

The data processing device of claim 13, wherein: said address generating circuit forms said predetermined combination of said source starting address and said source address value of said guide table entry pointed to by said table pointer by adding said source address value to said starting address.

Claim 20

The data processing device of claim 13, wherein: said address generating circuit forms said predetermined combination of said destination starting address and said destination address value of said guide table entry pointed to by said table pointer by adding said destination address value to said starting address.

Claim 21

The data processing device of claim 13, wherein: said source dimension values of each guide table entry comprise a horizontal source dimension value and a vertical source dimension value of an array of pixels; and said destination dimension values of each guide table entry comprise a horizontal destination dimension value and a vertical destination dimension value of an array of pixels.

Claim 22

An integrated circuit comprising on a single semiconductor chip: an internal memory storing data at a plurality of corresponding addresses, said plurality of addresses including a subset of internal addresses less than all possible addresses; an external memory interface operative to access external memory not included on said single semiconductor chip having addresses not within said subset of internal addresses, wherein said internal memory and external memory comprise a single address space; packet transfer parameters stored at a predetermined set of addresses in said internal memory, said packet transfer parameters including an indication of a number of guide table entries and an initial table pointer indicating an address in said internal memory; a guide table including said number of guide table entries indicated in said packet transfer parameters, each guide table entry stored in said internal memory beginning at an initial address and including a source start address, a source address value and source dimension values defining a source block of addresses and a destination start address, a destination address value and destination dimension values defining a destination block of addresses, each guide table entry including a table pointer indicating an initial address of a next guide table entry, a first guide table entry having an initial address corresponding to said table pointer of said packet transfer parameters; and a data processor having circuitry for generating packet transfer requests; a data transfer controller connected to said internal memory and a said data processor, said data transfer controller including a control circuit operative to receive a packet transfer request and initiate a packet transfer; and an address generating circuit coupled to said control circuit and to said internal memory, said address generating circuit operative to receive said number of guide table entries and said table pointer from said packet transfer parameters, said address generating circuit forming a set of block of addresses for memory access corresponding said guide table entry by forming a source block start address from a predetermined combination of said source start address and said source address value of said guide table entry pointed to by said table pointer, said first source block start address being said start address, forming a block of source addresses from said source block start address and said source dimension values of said guide table entry pointed to by said table pointer, forming a destination block start address from a predetermined combination of said destination start address and said destination address value of said guide table entry pointed to by said table pointer, said first destination block start address being said start address, forming a block of destination addresses from said destination block start address and said destination dimension values of said guide table entry pointed to by said table pointer, performing a memory transfer of data from said block of source addresses to said block of destination addresses, and replacing said table pointer with said table pointer of said current guide table entry to point to a next entry in said guide table following said memory access if less memory accesses than said number of guide table entries have been performed; said address generating circuit generating addresses within both said subset of internal addresses of said internal memory and not within said subset of internal addresses corresponding to external memory, said address qeneratinq circuit accessing said external memory via said external memory interface.

Claim 23

An integrated circuit comprising on a single semiconductor chip: an internal memory storing data at a plurality of corresponding addresses, said plurality of addresses including a subset of internal addresses less than all possible addresses; an external memory interface operative to access external memory not included on said single semiconductor chip having addresses not within said subset of internal addresses, wherein said internal memory and external memory comprise a single address space; packet transfer parameters stored at a predetermined set of addresses in said internal memory, said packet transfer parameters including an indication of a number of guide table entries and an initial table pointer indicating an address in said internal memory; a guide table including said number of guide table entries indicated in said packet transfer parameters, each guide table entry stored in said internal memory beginning at an initial address and including a source start address, a source address value and source dimension values defining a source block of addresses and a destination start address, a destination address value and destination dimension values defining a destination block of addresses, each guide table entry including a table pointer indicating an initial address of a next guide table entry, a first guide table entry having an initial address corresponding to said table pointer of said packet transfer parameters; and a data processor having circuitry for generating packet transfer requests; a data transfer controller connected to said internal memory and a said data processor, said data transfer controller including a control circuit operative to receive a packet transfer request and initiate a packet transfer; and an address generating circuit coupled to said control circuit and to said internal memory, said address generating circuit operative to receive said number of guide table entries and said table pointer from said packet transfer parameters, said address generating circuit forming a set of block of addresses for memory access corresponding said guide table entry by forming a source block start address from a predetermined combination of said source start address and said source address value of said guide table entry pointed to by said table pointer, said first source block start address being said start address, forming a block of source addresses from said source block start address and said source dimension values of said guide table entry pointed to by said table pointer, forming a destination block start address from a predetermined combination of said destination start address and said destination address value of said guide table entry pointed to by said table pointer, said first destination block start address being said start address, forming a block of destination addresses from said destination block start address and said destination dimension values of said guide table entry pointed to by said table pointer, performing a memory transfer of data from said block of source addresses to said block of destination addresses, and replacing said table pointer with said table pointer of said current guide table entry to point to a next entry in said guide table following said memory access if less memory accesses than said number of guide table entries have been performed; said address generating circuit generating addresses within both said subset of internal addresses of said internal memory and not within said subset of internal addresses corresponding to external memory, said address qeneratinq circuit accessing said external memory via said external memory interface.

Claim 24

The integrated circuit of claim 19, wherein: said address generating circuit forms said predetermined combination of said source starting address and said source address value of said guide table entry pointed to by said table pointer by adding said source address value to said prior source block starting address.

Claim 25

The integrated circuit of claim 19, wherein: said address generating circuit forms said predetermined combination of said destination starting address and said destination address value of said guide table entry pointed to by said table pointer by adding maid destination address value to said prior destination block starting address.

Claim 26

The integrated circuit of claim 19, wherein: said address generating circuit forms said predetermined combination of said source starting address and said source address value of said guide table entry pointed to by said table pointer by adding said source address value to said starting address.

Claim 27

The integrated circuit of claim 19, wherein: said address generating circuit forms said predetermined combination of said destination starting address and said destination address value of said guide table entry pointed to by said table pointer by adding said destination address value to said starting address.

Claim 28

The integrated circuit of claim 19, wherein: said source dimension values of each guide table entry comprise a horizontal source dimension value and a vertical source dimension value of an array of pixels; and said destination dimension values of each guide table entry comprise a horizontal destination dimension value and a vertical destination dimension value of an array of pixels.