IC standard cell designed with embedded capacitors

Claim 2

An IC standard cell design comprising: (a) an IC chip; (b) spaced pairs of voltage supply lines for providing supply voltages for electronic components, the supply lines extending over the chip in columnar directions; (c) spaced rows of standard cells embedded in the chip, each cell having electronic components therein, each row extending between adjacent pairs of voltage supply lines, the standard cell at each end of each row being an end-cell, each end-cell being located under and connected to the adjoining pair of voltage supply lines; and (d) a plurality of decoupling capacitors respectively included in the respective end-cells of respective ones of said rows, each decoupling capacitor being connected between the pair of voltage supply lines to which the associated end-cell is connected; whereby a program for establishing continuous place-and-route interconnections between the standard cells in each row is compatible with automatically providing for decoupling of said cells from transient impulses on the voltage supply lines.

Claim 3

The standard cell design of claim 1, wherein each of said decoupling capacitors comprises a thin oxide capacitor.

Claim 4

The standard cell design of claim 1, wherein the voltage supply lines are implemented by a second layer of metal and the standard cells are connected to the voltage supply lines by a first layer of metal extending below the second layer.

Claim 5

The standard cell design of claim 3, wherein the decoupling capacitors each comprise a thin oxide capacitor.

Claim 6

The standard cell design of claim 2, wherein the plural decoupling capacitors each further comprise a thick oxide capacitor.

Claim 7

The standard cell design of claim 1, wherein the standard cells are built on a semiconductor substrate employing polysilicon MOS transistor gates, a substrate well, and a thin oxide as the gate oxide of the MOS transistor, said at least one of said plural decoupling capacitors comprising a lower electrode constituted by the substrate well, a thin oxide over the substrate well as the capacitor dielectric, and an upper electrode constituted by a polysilicon layer over the thin oxide.

Claim 8

The standard cell design of claim 6, further comprising a thick first insulator over the polysilicon layer, a first metal layer over the first insulator, a thick second insulator over the first metal layer, a second metal layer over the second insulator, first connections between first portions of the first metal layer and the substrate well, second connections between second portions of the first metal layer and the polysilicon layer, third connections between one of the voltage supply lines and the first portions of the first metal layer, fourth connections between the other of the voltage supply lines and the second portions of the first metal layer.

Claim 9

The standard cell design of claim 7, wherein the voltage supply lines are constituted of portions of the second metal layer.

Claim 10

The standard cell design of claim 8, wherein the first and second metal layers form with the intervening second insulator thick oxide capacitors connected to the upper and lower electrodes, respectively.

Claim 11

The standard cell design of claim 6, wherein each decoupling capacitor comprises two sections in parallel.

Claim 12

The standard cell design of claim 10, wherein the two sections form elongated rectangles extending parallel to the columnar directions of the voltage supply lines.

Claim 13

The standard cell design of claim 10, wherein the two sections form elongated rectangles extending transverse to the columnar directions of the voltage supply lines.

Claim 14

An IC standard cell design comprising an IC chip, a spaced pair of voltage supply lines for providing supply voltage for electronic components and extending over the chip in columnar directions, spaced rows of standard cells embedded in the chip and extending between and connected to adjacent pairs of voltage supply lines, wherein the standard cells are built on a semiconductor substrate employing polysilicon MOS transistor gates, a substrate well, and a thin oxide as the gate oxide of the MOS transistor, and plural decoupling capacitors comprising a first thin film capacitor including, a first electrode constituted by the substrate well, a thin oxide over the substrate well as the capacitor dielectric, and a second electrode constituted by a polysilicon layer over the thin oxide, and a second thick film capacitor comprising a thick first insulator over the polysilicon layer, a first metal layer over the thick first insulator, a thick second insulator over the first metal layer, a second metal layer over the thick second insulator, first connections between first portions of the first metal layer and the substrate well, second connections between second portions of the first metal layer and the polysilicon layer, third connections between one of the voltage supply lines and the first portions of the first metal layer, fourth connections between the other of the voltage supply lines and the second portions of the first metal layer.

Claim 15

An IC standard cell design comprising an IC chip, a spaced pair of voltage supply lines for providing supply voltage for electronic components and extending over the chip in columnar directions, spaced rows of standard cells embedded in the chip and extending between and connected to adjacent pairs of voltage supply lines, wherein the standard cells are built on a semiconductor substrate employing polysilicon MOS transistor gates, a substrate well, and a thin oxide as the gate oxide of the MOS transistor, and plural decoupling capacitors comprising a first thin film capacitor including, a first electrode constituted by the substrate well, a thin oxide over the substrate well as the capacitor dielectric, and a second electrode constituted by a polysilicon layer over the thin oxide, and a second thick film capacitor comprising a thick first insulator over the polysilicon layer, a first metal layer over the thick first insulator, a thick second insulator over the first metal layer, a second metal layer over the thick second insulator, first connections between first portions of the first metal layer and the substrate well, second connections between second portions of the first metal layer and the polysilicon layer, third connections between one of the voltage supply lines and the first portions of the first metal layer, fourth connections between the other of the voltage supply lines and the second portions of the first metal layer.

Claim 16

The standard cell design of claim 13, wherein the voltage supply lines are constituted of portions of the second metal layer.

Claim 17

The standard cell design of claim 13, wherein the first and second metal layers form with the intervening second insulator thick oxide capacitors connected to the first and second electrodes, respectively.

Claim 18

The standard cell design of claim 13, wherein each decoupling capacitor comprises two sections in parallel.

Claim 19

The standard cell design of claim 16, wherein the two sections form elongated rectangles extending parallel to the columnar directions of the voltage supply lines.

Claim 20

The standard cell design of claim 16, wherein the two sections form elongated rectangles extending transverse to the columnar directions of the voltage supply lines.

Claim 21

An IC capacitor comprising: (a) a substantially rectangular IC chip having a silicon substrate, a diffusion layer formed in a well in a surface of said substrate, a thin oxide layer formed over said diffusion layer, and a polysilicon layer formed over said oxide layer; (b) a spaced pair of voltage supply lines extending in parallel and respectively adjoining opposite edges of said chip; (c) each of said supply lines having a series of spaced finger portions extending transversely thereto over said chip, the finger portions of each supply line being inter-digitated between but separate from the finger portions of the other of said supply lines; (d) a series of via contacts along each of said finger portions, the via contacts of a first of said supply lines being in electrical contact with said diffusion layer of the chip, the via contacts of a second of said supply lines being in electrical contact with said polysilicon layer of the chip; said diffusion layer and polysilicon layer thereby constituting opposite electrodes of a capacitor having said oxide layer as a dielectric, and the finger portions of said supply lines constituting a plurality of low resistance parallel interconnections between said electrodes and said supply lines; whereby said capacitor and said low resistance connections provide a low RC time constant path for decoupling the chip from transient impulses on either of the supply lines.

Claim 22

An IC capacitor comprising: (a) a substantially rectangular IC chip having a silicon substrate, a diffusion layer formed in a well in a surface of said substrate, a thin oxide layer formed over said diffusion layer, and a polysilicon layer formed over said oxide layer; (b) a spaced pair of voltage supply lines extending in parallel and respectively adjoining opposite edges of said chip; (c) each of said supply lines having a series of spaced finger portions extending transversely thereto over said chip, the finger portions of each supply line being inter-digitated between but separate from the finger portions of the other of said supply lines; (d) a series of via contacts along each of said finger portions, the via contacts of a first of said supply lines being in electrical contact with said diffusion layer of the chip, the via contacts of a second of said supply lines being in electrical contact with said polysilicon layer of the chip; said diffusion layer and polysilicon layer thereby constituting opposite electrodes of a capacitor having said oxide layer as a dielectric, and the finger portions of said supply lines constituting a plurality of low resistance parallel interconnections between said electrodes and said supply lines; whereby said capacitor and said low resistance connections provide a low RC time constant path for decoupling the chip from transient impulses on either of the supply lines.