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US5707883A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for manufacturing a semiconductor device using antireflection coating

Assignee: Yamaha Corp
•
Filing: 1995-05-31
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Granted: 1998-01-13
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Expires: 2015-05-31
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Abstract

Abstract A conductive film is formed overlying an insulating film overlying the surface of a semiconductor substrate, the conductive film being made, for example, of a material such as polysilicon, WSi2, Al and Al alloy, and the like. An antireflection film, made of silicon nitride, for example, is formed overlying the surface of the conductive film, the antireflection film reducing light scattering from the conductive film and having a lower etching rate than the etching rate of the conductive film. The antireflection film is patterned to provide a mask for etching the conductive film, and the conductive film is etched using the patterned antireflection film as a mask to form a gate electrode for an MOS transistor, for example. Source and drain regions, for the MOS transistor, for example, are formed in the semiconductor substrate, and an interlayer insulating film is formed overlying the insulating film overlying the semiconductor substrate, the gate electrode and the antireflection film mask remaining on the surface of the gate electrode. The interlayer insulating film is selectively etched to form a deep contact hole, piercing to the semiconductor substrate in the source region, for example, and a shallow contact hole, piercing to the gate electrode. The antireflection film mask remaining on the surface of the gate electrode retards the etching of the shallow contact hole so that the etchings of the shallow contact hole and of the deep contact hole are completed substantially simultaneously.

Inventors

  • 👤 Suguru Tabara

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 19:41
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; H10P76/2043; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 222 words
A method for manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor body; (b) forming thick insulating regions on a surface of the semiconductor body, each of the regions having a horizontal plane and a slope adjacent to the horizontal plane; (c) forming a conductive film overlying the surface of the semiconductor body, the conductive film having an undulation due to he slope of the thick insulating regions; (d) forming an antireflection film overlying the surface of the conductive film, the antireflection film reducing light scattering from the conductive film and having a lower etching rate than an etching rate of the conductive film; (e) patterning the antireflection film to provide a mask for etching the conductive film; (f) etching the conductive film using the patterned antireflection film as a mask to form an electrode; (g) forming a source region and a drain region on the semiconductor body; (h) forming an interlayer insulating layer overlying the semiconductor body, the electrode and the mask; and (i) selectively etching the interlayer insulating layer to form a deep contact hole piercing to the semiconductor body and a shallow contact hole piercing to the electrode, wherein the mask provided on the electrode retards etching of the electrode to complete the etching of the deep contact hole and the shallow contact hole substantially coincidentally.
Claim 2
Independent Claim 222 words
A method for manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor body; (b) forming thick insulating regions on a surface of the semiconductor body, each of the regions having a horizontal plane and a slope adjacent to the horizontal plane; (c) forming a conductive film overlying the surface of the semiconductor body, the conductive film having an undulation due to he slope of the thick insulating regions; (d) forming an antireflection film overlying the surface of the conductive film, the antireflection film reducing light scattering from the conductive film and having a lower etching rate than an etching rate of the conductive film; (e) patterning the antireflection film to provide a mask for etching the conductive film; (f) etching the conductive film using the patterned antireflection film as a mask to form an electrode; (g) forming a source region and a drain region on the semiconductor body; (h) forming an interlayer insulating layer overlying the semiconductor body, the electrode and the mask; and (i) selectively etching the interlayer insulating layer to form a deep contact hole piercing to the semiconductor body and a shallow contact hole piercing to the electrode, wherein the mask provided on the electrode retards etching of the electrode to complete the etching of the deep contact hole and the shallow contact hole substantially coincidentally.
Claim 3
Dependent Claim 36 words
A method for manufacturing the semiconductor device according to claim 1, further comprising: (j) forming a second conductive film overlying the interlayer insulating layer; and (k) forming a second antireflection film overlying the second conductive film.
Claim 4
Dependent Claim 30 words
A method for manufacturing the semiconductor device according to claim 1, wherein the forming step (d) provides a silicon nitride film formed on the conductive film as the antireflection film.
Claim 5
Dependent Claim 28 words
A method for manufacturing the semiconductor device according to claim 1, wherein the forming step (d) provides the antireflection film having a thickness of 50 to 60 nm.
Claim 6
Dependent Claim 24 words
A method for manufacturing the semiconductor device according to claim 1, wherein the forming step (c) provides an aluminum film as the conductive film.
Claim 7
Dependent Claim 22 words
A method for manufacturing the semiconductor device according to claim 1, wherein the etching step (f) is free of a resist layer.

References Cited (Backward Citations)

US4820611A Cited
US4885259A Cited
JPH01241125A Cited
US5561084A Cited
US5326431A Cited
JPH0555130A Cited
US5298463A Cited
US5399527A Cited
US5286344A Cited
US5403781A Cited
US5451543A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-01-12 2001-07-14 2002-01-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-01-12 2005-07-14 2006-01-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-01-12 2009-07-14 2010-01-13 $7700.00 Window Closed / Lapsed

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