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US5715435A
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Trace control circuit in emulation system
Assignee: NEC Corp
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Filing: 1996-05-24
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Granted: 1998-02-03
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Expires: 2016-05-24
Abstract
Abstract In a trace control circuit for an emulation system, a program fetch signal is generated on the basis of a CPU read signal and a CPU program fetch status signal, both generated from the CPU included in the trace control circuit, and then, is thinned out at an arbitrary proportion so as to generate a trace memory write signal to a trace memory, so that a trace imformation outputted from the CPU is stored in a trace memory in response to the trace memory write signal thus generated. Accordingly, the memory capacity of the trace memory can be apparently increased.
Inventors
- 👤 Satoshi Ikei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
135 words
An emulation system having a trace control means which at least comprises: a CPU having an operation function equivalent to that of a microcomputer which executes a program to be analyzed and evaluated; a trace memory storing a trace data outputted from said CPU in response to a trace memory write signal, said trace memory outputting said trace data stored therein in response to a trace memory read signal; a trace memory write signal generating circuit receiving a CPU read signal outputted from said CPU and a program fetch status signal outputted from said CPU and indicating that a program fetch cycle is generated in said CPU, for generating said trace memory write signal to said trace memory; and a trace memory control circuit for generating said trace memory read signal to said trace memory.
Claim 2
Dependent Claim
135 words
An emulation system having a trace control means which at least comprises: a CPU having an operation function equivalent to that of a microcomputer which executes a program to be analyzed and evaluated; a trace memory storing a trace data outputted from said CPU in response to a trace memory write signal, said trace memory outputting said trace data stored therein in response to a trace memory read signal; a trace memory write signal generating circuit receiving a CPU read signal outputted from said CPU and a program fetch status signal outputted from said CPU and indicating that a program fetch cycle is generated in said CPU, for generating said trace memory write signal to said trace memory; and a trace memory control circuit for generating said trace memory read signal to said trace memory.
Claim 3
Dependent Claim
55 words
An emulation system claimed in claim 1 wherein said trace memory write signal generating circuit includes: a logical sum circuit receiving said CPU read signal and said program fetch status signal, for outputting a CPU program fetch signal; and a modulating circuit receiving said CPU program fetch signal, for outputting said trace memory write signal.
Claim 4
Dependent Claim
61 words
An emulation system claimed in claim 2 wherein said modulating circuit includes: a frequency-divider receiving said CPU program fetch signal, for outputting a plurality of frequency-divided signals obtained by frequency-dividing said CPU program fetch signal; and a selector receiving said plurality of frequency-divided signals, for outputting a selected one of said plurality of frequency-divided signals as said trace memory write signal.
Claim 5
Dependent Claim
114 words
An emulation system claimed in claim 2 wherein said modulating circuit includes: a timer counter receiving and counting a system clock, for outputting a timer counter overflow signal when a count value reaches a value corresponding to a predetermined counting time: a flip flop receiving said timer counter overflow signal and said CPU program fetch signal, for outputting a timer counter initializing signal to said timer counter so as to initialize said timer counter; and a logical sum circuit receiving said timer counter overflow signal and said CPU program fetch signal, for outputting a logical sum of said timer counter overflow signal and said CPU program fetch signal, as said trace memory write signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-02 | 2001-08-04 | 2002-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-02 | 2005-08-04 | 2006-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-02 | 2009-08-04 | 2010-02-03 | $7700.00 | Window Closed / Lapsed |