Multilayer amorphous silicon antifuse

Claim 2

An antifuse comprising: first and second conductive layers; and an antifuse layer, positioned between the first and second conductive layers, having a thickness of less than about 100 nm, the antifuse layer including first and second undoped amorphous silicon layers and an oxide layer positioned between the first and second undoped amorphous silicon layers, wherein the oxide layer has a thickness of less than about 10 nm.

Claim 3

An antifuse according to claim 1 wherein the antifuse layer has a thickness of less than about 85 nm.

Claim 4

An antifuse according to claim 1 wherein the antifuse layer has a thickness of between about 20 and 85 nm.

Claim 5

An antifuse according to claim 1 wherein the oxide layer has opposing first and second surfaces, the first undoped amorphous silicon layer being in contact with the first surface and the second undoped amorphous silicon layer being in contact with the second surface.

Claim 6

An antifuse according to claim 1 wherein the oxide layer has a thickness of between about 1 and 10 nm.

Claim 7

An antifuse according to claim 1 wherein the oxide layer is grown from the amorphous silicon layer.

Claim 8

An antifuse according to claim 6 wherein the oxide layer is grown by a high dose Ar+ implant.

Claim 9

An antifuse according to claim 6 wherein the oxide layer is grown by an oxygen plasma.

Claim 10

An antifuse according to claim 6 wherein the oxide layer is formed by a self-limiting growth process.

Claim 11

An antifuse according to claim 1 wherein the amorphous silicon layer is formed in mole percentages of between about 8-12% H and between about 10-25% N.

Claim 12

An interconnect structure for interconnecting logic blocks in a programmable logic device comprising: a plurality of antifuses, at least one antifuse including first and second conductive layers and an antifuse layer having a thickness of less than about 100 nm positioned between the first and second conductive layers, the antifuse layer including first and second undoped amorphous silicon layers and an oxide layer positioned between the first and second undoped amorphous silicon layers, wherein the oxide layer has a thickness of less than about 10 nm ; and a plurality of interconnect lines, each line connected to at least one antifuse at either the first or second conductive layer of the antifuse.

Claim 13

An interconnect structure for interconnecting logic blocks in a programmable logic device comprising: a plurality of antifuses, at least one antifuse including first and second conductive layers and an antifuse layer having a thickness of less than about 100 nm positioned between the first and second conductive layers, the antifuse layer including first and second undoped amorphous silicon layers and an oxide layer positioned between the first and second undoped amorphous silicon layers, wherein the oxide layer has a thickness of less than about 10 nm ; and a plurality of interconnect lines, each line connected to at least one antifuse at either the first or second conductive layer of the antifuse.

Claim 14

An interconnect structure according to claim 11 wherein the antifuse layer has a thickness of less than about 85 nm.

Claim 15

An interconnect structure according to claim 11 wherein the antifuse layer has a thickness of between about 20 and 85 nm.

Claim 16

An interconnect structure according to claim 11 wherein the oxide layer has opposing first and second surfaces, the first undoped amorphous silicon layer being in contact with the first surface and the second undoped amorphous silicon layer being in contact with the second surface.

Claim 17

An interconnect structure according to claim 11 wherein the antifuse layer includes at least two oxide layers and at least three undoped amorphous silicon layers, each of the two oxide layers being positioned between a pair of undoped amorphous silicon layers.

Claim 18

An interconnect structure according to claim 11 wherein the oxide layer has a thickness of between about 1 and 10 nm.

Claim 19

An interconnect structure according to claim 11 wherein the plurality of antifuses are programmed by a range of programing voltages, the range forming a distribution having a standard deviation of less than about 0.30.

Claim 20

An interconnect structure according to claim 17 wherein the distribution of programing voltages has a standard deviation of less than about 0.20.

Claim 21

An interconnect structure according to claim 13 wherein the oxide layer is grown from the amorphous silicon layer.

Claim 22

An interconnect structure according to claim 19 wherein the oxide layer is formed by a self-limiting growth process.

Claim 23

A programmable logic device comprising: a plurality of logic blocks; an interconnect structure attached to each of the logic blocks for interconnecting two or more of the plurality of logic blocks, the interconnect structure including a plurality of antifuses, at least one antifuse including first and second conductive layers and an antifuse layer having a thickness of less than about 100 nm positioned between the first and second conductive layers, the antifuse layer including first and second undoped amorphous silicon layers and an oxide layer positioned between the first and second undoped amorphous silicon layers, wherein the oxide layer has a thickness of less than about 10 nm, and a plurality of interconnect lines, each line connected to at least one antifuse at either the first or second conductive layer of the antifuse.

Claim 24

A programmable logic device comprising: a plurality of logic blocks; an interconnect structure attached to each of the logic blocks for interconnecting two or more of the plurality of logic blocks, the interconnect structure including a plurality of antifuses, at least one antifuse including first and second conductive layers and an antifuse layer having a thickness of less than about 100 nm positioned between the first and second conductive layers, the antifuse layer including first and second undoped amorphous silicon layers and an oxide layer positioned between the first and second undoped amorphous silicon layers, wherein the oxide layer has a thickness of less than about 10 nm, and a plurality of interconnect lines, each line connected to at least one antifuse at either the first or second conductive layer of the antifuse.

Claim 25

A programmable logic device according to claim 21 wherein the antifuse layer has a thickness of less than about 85 nm.

Claim 26

A programable logic device according to claim 21 wherein the antifuse layer has a thickness of between about 20 and 85 nm.

Claim 27

A programmable logic device according to claim 21 wherein the oxide layer has opposing first and second surfaces, the first undoped amorphous silicon layer being in contact with the first surface and the second undoped amorphous silicon layer being in contact with the second surface.

Claim 28

A programmable logic device according to claim 21 wherein the antifuse layer includes at least two oxide layers and at least three undoped amorphous silicon layers, each of the two oxide layers being positioned between a pair of undoped amorphous silicon layers.

Claim 29

A programable logic device according to claim 21 wherein the oxide layer has a thickness of between about 1 and 10 nm.

Claim 30

A programable logic device according to claim 21 wherein the plurality of antifuses are programmed by a range of programing voltages, the range forming a distribution having a standard deviation of less than about 0.30.

Claim 31

A programable logic device according to claim 27 wherein the distribution of programing voltages has a standard deviation of less than about 0.20.

Claim 32

A programable logic device according to claim 21 wherein the oxide layer is grown from the amorphous silicon layer.

Claim 33

A programable logic device according to claim 29 wherein the oxide layer is formed by a self-limiting growth process.