US5726931A
Expired / Lapsed
US
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DRAM with open digit lines and array edge reference sensing
Assignee: Round Rock Research LLC
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Filing: 1997-02-20
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Granted: 1998-03-10
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Expires: 2017-02-20
Abstract
Abstract A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a reference while the other digit line is active. A reference circuit is described which can be used to replace one of the digit lines connected to the sense amplifier circuit. The reference circuit models the electrical characteristics of a digit line by including a capacitor and a transistor, each sized to match the characteristics of a digit line.
Inventors
- 👤 Paul S. Zagar
- 👤 Mirmajid Seyyedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:31
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C11/4099; G11C7/14
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
160 words
An integrated memory device comprising: an array of memory cells; addressing circuitry for receiving an address of the memory cells; and control circuitry for controlling read and write operations of the memory device; the array of memory cells comprising: memory cell capacitors having a first plate and a second plate, the first plate being coupled to a reference voltage and the second plate being coupled to a digit line through an n-channel access transistor, the access transistor being controlled by a word line voltage, and a sense amplifier having a first input selectively coupled to the digit line and having a second input selectively coupled to a reference circuit for modeling electrical characteristics of the digit line, the reference circuit comprising: a plurality of compensating capacitors having a first plate coupled to the sense amplifier and a second plate coupled to a capacitor reference voltage, and an n-channel transistor having a gate coupled to receive an inactive word line voltage.
Claim 2
Dependent Claim
160 words
An integrated memory device comprising: an array of memory cells; addressing circuitry for receiving an address of the memory cells; and control circuitry for controlling read and write operations of the memory device; the array of memory cells comprising: memory cell capacitors having a first plate and a second plate, the first plate being coupled to a reference voltage and the second plate being coupled to a digit line through an n-channel access transistor, the access transistor being controlled by a word line voltage, and a sense amplifier having a first input selectively coupled to the digit line and having a second input selectively coupled to a reference circuit for modeling electrical characteristics of the digit line, the reference circuit comprising: a plurality of compensating capacitors having a first plate coupled to the sense amplifier and a second plate coupled to a capacitor reference voltage, and an n-channel transistor having a gate coupled to receive an inactive word line voltage.
Claim 3
Dependent Claim
15 words
The integrated memory device of claim 1 wherein the capacitor reference voltage is ground potential.
Claim 4
Dependent Claim
17 words
The integrated memory device of claim 1 wherein the capacitor reference voltage is a substrate bias voltage.
Claim 5
Dependent Claim
99 words
An integrated memory circuit having an open digit line architecture comprising: a memory array comprising memory cells arranged in rows and columns; a plurality of sense amplifier circuits located within the memory array and coupled to oppositely extending first and second active digit lines; and a plurality of peripheral sense amplifier circuits located within the memory array and along an edge of the memory array, the peripheral sense amplifier circuits having first node coupled to a third active digit line, and a second node coupled to a reference circuit for modeling electrical characteristics of the third active digit line.
Claim 6
Dependent Claim
99 words
An integrated memory circuit having an open digit line architecture comprising: a memory array comprising memory cells arranged in rows and columns; a plurality of sense amplifier circuits located within the memory array and coupled to oppositely extending first and second active digit lines; and a plurality of peripheral sense amplifier circuits located within the memory array and along an edge of the memory array, the peripheral sense amplifier circuits having first node coupled to a third active digit line, and a second node coupled to a reference circuit for modeling electrical characteristics of the third active digit line.
Claim 7
Dependent Claim
50 words
The integrated memory circuit of claim 4 wherein the reference circuit comprises: a reference line coupled to the second node of the plurality of peripheral sense amplifier circuits; and a capacitor having a first plate connected to the reference line and a second plate connected to receive a reference voltage.
Claim 8
Dependent Claim
39 words
The integrated memory circuit of claim 5 wherein the reference circuit further comprises: a transistor connected to the reference line, the transistor having a drain connected to the reference line and a gate connected to the inactive voltage level.
Claim 9
Dependent Claim
21 words
The integrated memory circuit of claim 6 wherein the transistor is sized to model access transistors coupled to the digit line.
Claim 10
Dependent Claim
20 words
The integrated memory circuit of claim 5 wherein the capacitor is sized to model parasitic capacitance of the digit line.
Claim 11
Dependent Claim
18 words
The integrated memory circuit of claim 5 further comprising a voltage bias circuit coupled to the reference line.
Claim 12
Independent Claim
74 words
A method of providing a reference voltage to a differential sense amplifier in a memory device, the sense amplifier having a first node and a second node coupled to an active digit line, the method comprising the steps of: charging a reference circuit to the reference voltage, the reference circuit comprising a capacitor for modeling electrical characteristics of the digit line; and coupling the reference circuit to the first node of the sense amplifier.
Claim 13
Independent Claim
74 words
A method of providing a reference voltage to a differential sense amplifier in a memory device, the sense amplifier having a first node and a second node coupled to an active digit line, the method comprising the steps of: charging a reference circuit to the reference voltage, the reference circuit comprising a capacitor for modeling electrical characteristics of the digit line; and coupling the reference circuit to the first node of the sense amplifier.
Claim 14
Dependent Claim
13 words
The method of claim 10 wherein the capacitor comprises a plurality of capacitors.
Claim 15
Dependent Claim
13 words
The method of claim 10 wherein the reference circuit further comprises a transistor.
Claim 16
Independent Claim
110 words
A method of fabricating a memory array in a memory device having an open digit line architecture, the method comprising the steps of: fabricating first and second active digit lines coupled to sense amplifiers located within the memory array, the first and second digit lines extending in opposite directions from the sense amplifiers; and fabricating a third active digit line and a reference circuit comprising a capacitor for modeling electrical characteristics of the third active digit line to extend in opposite directions from sense amplifiers located in the memory array and along an edge of the memory array, the reference circuit located adjacent to the edge of the memory array.
Claim 17
Independent Claim
110 words
A method of fabricating a memory array in a memory device having an open digit line architecture, the method comprising the steps of: fabricating first and second active digit lines coupled to sense amplifiers located within the memory array, the first and second digit lines extending in opposite directions from the sense amplifiers; and fabricating a third active digit line and a reference circuit comprising a capacitor for modeling electrical characteristics of the third active digit line to extend in opposite directions from sense amplifiers located in the memory array and along an edge of the memory array, the reference circuit located adjacent to the edge of the memory array.
Claim 18
Dependent Claim
13 words
The method of claim 13 wherein the capacitor comprises a plurality of capacitors.
Claim 19
Dependent Claim
13 words
The method of claim 13 wherein the reference circuit further comprises a transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-09 | 2001-09-08 | 2002-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-09 | 2005-09-08 | 2006-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-09 | 2009-09-08 | 2010-03-10 | $7700.00 | Window Closed / Lapsed |