Data read circuit for a nonvolatile semiconductor memory

Claim 2

A data read circuit for a nonvolatile semiconductor memory having at least one bit line, and a plurality of memory transistors connected to said bit line, said circuit comprising: at least one data sense line; a precharge voltage circuit connected between said bit line and said data sense line, said precharge voltage circuit providing a precharge voltage on said bit line having a preselected precharge level; a current supplying circuit which supplies a precharge current to said data sense line such that said bit line is precharged to said preselected precharge level in correspondence with said precharge voltage circuit, and which supplies a sense current to said data sense line such that the voltage variation of the bit line from said preselected precharge level based on data stored in a selected one of said memory transistors connected to said bit line is amplified in accordance with the corresponding voltage variation of said data sense line; and a sense amplifier coupled to said data sense line which senses and latches said stored data according to said amplified voltage variation.

Claim 3

The data read circuit according to claim 1, wherein said preselected precharge level is lower than a power supply voltage level.

Claim 4

The data read circuit according to claim 1, wherein said sense current is lower than said precharge current.

Claim 5

The data read circuit according to claim 1, wherein said precharge voltage circuit comprises a transistor connected between said bit line and said data sense line and a reference voltage generating circuit which supplies a reference voltage to a control gate of said transistor.

Claim 6

The data read circuit according to claim 4, wherein said precharge voltage level is less than the level of said reference voltage.

Claim 7

The data read circuit according to claim 4, wherein said transistor is an N-type transistor.

Claim 8

The data read circuit according to claim 1, wherein said precharge voltage level is less than one third the level of said power supply voltage.

Claim 9

The data read circuit according to claim 1, wherein the corresponding voltage variation on said data sense line amplifies the voltage variation on said bit line based upon a ratio of a parasitic capacitance of said bit line to a parasitic capacitance of said data sense line.

Claim 10

The data read circuit according to claim 8, wherein said bit line parasitic capacitance is greater than said data sense line parasitic capacitance.

Claim 11

The data read circuit according to claim 1, wherein said current supply circuit supplies said precharge current and said sense current in response to a precharge control signal.

Claim 12

The data read circuit according to claim 10, wherein said current supply circuit is a current mirror type.

Claim 13

The data read circuit according to claim 4, wherein the level of said reference voltage is approximately equal to a trip voltage level of said sense amplifier.

Claim 14

A data read circuit for a nonvolatile semiconductor memory having a plurality of bit lines and a plurality of NAND cell units connected to each of said bit lines, each NAND cell unit including a plurality of series-connected memory transistors, said circuit comprising: a plurality of data sense lines; a plurality of transistors, each of said transistors having a channel connected between a corresponding one of said bit lines and a corresponding one of said data sense lines; a reference voltage generating circuit which supplies a preselected voltage level to gates of each of said plurality of transistors; a current supplying circuit which supplies a precharge current to each of said data sense lines such that said each bit line is precharged to a precharge voltage level lower than said preselected voltage level in correspondence with said reference voltage generating circuit, and such that each of said data sense lines is precharged to a power supply voltage level, said current supplying circuit also supplying a sense current lower than said precharge current to each of said data sense lines such that the voltage variation from said precharge voltage level according to data stored in selected ones of said memory transistors within selected NAND cell units connected to corresponding ones of each of said bit lines is amplified in accordance with the corresponding voltage variation from said power supply voltage level on said corresponding ones of said data sense lines; and a plurality of sense amplifiers respectively connected to each of said data sense lines, which sense and latch said stored data according to the corresponding amplified voltage variation on said each of said data sense lines.

Claim 15

A data read circuit for a nonvolatile semiconductor memory having a plurality of bit lines and a plurality of NAND cell units connected to each of said bit lines, each NAND cell unit including a plurality of series-connected memory transistors, said circuit comprising: a plurality of data sense lines; a plurality of transistors, each of said transistors having a channel connected between a corresponding one of said bit lines and a corresponding one of said data sense lines; a reference voltage generating circuit which supplies a preselected voltage level to gates of each of said plurality of transistors; a current supplying circuit which supplies a precharge current to each of said data sense lines such that said each bit line is precharged to a precharge voltage level lower than said preselected voltage level in correspondence with said reference voltage generating circuit, and such that each of said data sense lines is precharged to a power supply voltage level, said current supplying circuit also supplying a sense current lower than said precharge current to each of said data sense lines such that the voltage variation from said precharge voltage level according to data stored in selected ones of said memory transistors within selected NAND cell units connected to corresponding ones of each of said bit lines is amplified in accordance with the corresponding voltage variation from said power supply voltage level on said corresponding ones of said data sense lines; and a plurality of sense amplifiers respectively connected to each of said data sense lines, which sense and latch said stored data according to the corresponding amplified voltage variation on said each of said data sense lines.

Claim 16

The data read circuit according to claim 13, wherein said reference voltage generating circuit supplies said preselected voltage such that said precharge voltage level on each of said bit lines is less than one third of said power supply voltage level.

Claim 17

A nonvolatile semiconductor memory comprising: at least one bit line; a plurality of memory transistors connected to said bit line; at least one data sense line; a precharge voltage circuit connected between said bit line and said data sense line, said precharge voltage circuit providing a precharge voltage on said bit line having a preselected precharge level; a current supplying circuit which supplies a precharge current to said data sense line such that said bit line is precharged to said preselected precharge level in correspondence with said precharge voltage circuit, and which supplies a sense current to said data sense line such that the voltage variation of the bit line from said preselected precharge level based on data stored in a selected one of said memory transistors connected to said bit line is amplified in accordance with the corresponding voltage variation of said data sense line; and a sense amplifier coupled to said data sense line which senses and latches said stored data according to said amplified voltage variation.

Claim 18

A nonvolatile semiconductor memory comprising: at least one bit line; a plurality of memory transistors connected to said bit line; at least one data sense line; a precharge voltage circuit connected between said bit line and said data sense line, said precharge voltage circuit providing a precharge voltage on said bit line having a preselected precharge level; a current supplying circuit which supplies a precharge current to said data sense line such that said bit line is precharged to said preselected precharge level in correspondence with said precharge voltage circuit, and which supplies a sense current to said data sense line such that the voltage variation of the bit line from said preselected precharge level based on data stored in a selected one of said memory transistors connected to said bit line is amplified in accordance with the corresponding voltage variation of said data sense line; and a sense amplifier coupled to said data sense line which senses and latches said stored data according to said amplified voltage variation.

Claim 19

The nonvolatile semiconductor memory according to claim 15, wherein said precharge voltage circuit comprises a transistor connected between said bit line and said data sense line and a reference voltage generating circuit which supplies a reference voltage to a control gate of said transistor.

Claim 20

The nonvolatile semiconductor memory according to claim 16, wherein said precharge voltage level is less than the level of said reference voltage.

Claim 21

The nonvolatile semiconductor memory according to claim 15, wherein the corresponding voltage variation on said data sense line amplifies the voltage variation on said bit line based upon a ratio of a parasitic capacitance of said bit line to a parasitic capacitance of said data sense line.

Claim 22

The nonvolatile semiconductor memory according to claim 18, wherein said bit line parasitic capacitance is greater than said data sense line parasitic capacitance.

Claim 23

The nonvolatile semiconductor memory according to claim 15, wherein said current supply circuit supplies said precharge current and said sense current in response to a precharge control signal.

Claim 24

A data read circuit in a semiconductor memory having at least one bit line and at least one memory transistor connected to said bit line, said semiconductor memory including a precharge mode defined by a precharge signal and a sensing mode defined by a sensing signal, said data read circuit comprising: a precharge voltage circuit that provides a precharge voltage having a preselected precharge level to said bit line in response to said precharge signal; and a current supply circuit that supplies a precharge current in response to said precharge signal such that said bit line is charged to said preselected precharge level, and that supplies a sensing current different than said precharge current in response to said sensing signal, such that the voltage on said bit line varies from said preselected precharge level in accordance with data stored in said memory transistor.

Claim 25

A data read circuit in a semiconductor memory having at least one bit line and at least one memory transistor connected to said bit line, said semiconductor memory including a precharge mode defined by a precharge signal and a sensing mode defined by a sensing signal, said data read circuit comprising: a precharge voltage circuit that provides a precharge voltage having a preselected precharge level to said bit line in response to said precharge signal; and a current supply circuit that supplies a precharge current in response to said precharge signal such that said bit line is charged to said preselected precharge level, and that supplies a sensing current different than said precharge current in response to said sensing signal, such that the voltage on said bit line varies from said preselected precharge level in accordance with data stored in said memory transistor.

Claim 26

The data read circuit according to claim 21, wherein said current supply circuit includes: a current source transistor coupled between a power supply and said bit line, said current source transistor having a control gate; a precharge control circuit coupled to said control gate, said precharge control circuit receiving said precharge signal and causing said current source transistor to supply said precharge current in response thereto; and a sensing control circuit coupled to said control gate, said sensing control circuit receiving said sensing signal and causing said current source transistor to supply said sensing current in response thereto.