Patent US3318145A successfully refreshed from Google Patents.
US5757699A
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Programming which can make threshold voltages of programmed memory cells have a narrow distribution in a nonvolatile semiconductor memory
Assignee: Renesas Electronics Corp
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Filing: 1997-06-03
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Granted: 1998-05-26
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Expires: 2017-06-03
Abstract
Abstract On programming a selected memory cell of a nonvolatile semiconductor memory, first programming (S11) of the selected memory cell is made by applying a first programming pulse to the selected memory cell to make the selected memory cell have a programmed threshold voltage (Vtm). First verification (S12) is made whether the selected memory cell has the programmed threshold voltage which is not greater than a first predetermined upper limit voltage (Vt1). When the selected memory cell has the programmed threshold voltage greater than the Vt1, the first programming is again made. When the selected memory cell has the programmed threshold voltage not greater than the Vt1, second verification (S13) is made whether the selected memory cell has the programmed threshold voltage which is not greater than a second predetermined upper limit voltage (Vt10) less than the Vt1. When the selected memory cell has the programmed threshold voltage greater than the Vt10, second programming (S13) of the selected memory cell by applying a second programming pulse different from the first programming pulse to the selected memory cell so as to make the selected memory cell have the programmed threshold voltage which is not greater than the Vt10. When the selected memory cell has the programmed threshold voltage not greater than the Vt10, programming of the selected memory cell is completed.
Inventors
- 👤 Toshio Takeshima
- 👤 Hiroshi Sugawara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:19
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
346 words
A method of programming a selected memory cell of electrically erasable and programmable nonvolatile memory cells of a nonvolatile semiconductor memory in response to an input datum of a particular logic level, said method comprising: a first programming step of programming said selected memory cell in response to said input datum by applying a first programming pulse to said selected memory cell to make said selected memory cell have a programmed threshold voltage; a first verifying step of verifying whether said selected memory cell has the programmed threshold voltage which is not greater than a first predetermined upper limit voltage; a re-executing step of re-executing said first programming step when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is greater than said first predetermined upper limit voltage, said re-executing step being carried out until said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said first predetermined upper limit voltage; a second verifying step of verifying, when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said first predetermined upper limit voltage, whether said selected memory cell has the programmed threshold voltage which is not greater than a second predetermined upper limit voltage less than said first predetermined upper limit voltage; a second programming step of programming, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is greater than said second predetermined upper limit voltage, said selected memory cell by applying a second programming pulse different from said first programming pulse to said selected memory cell so as to make said selected memory cell have the programmed threshold voltage which is not greater than said second predetermined upper limit voltage; and a completion step of completing programming of said selected memory cell when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said second predetermined upper limit voltage.
Claim 2
Independent Claim
346 words
A method of programming a selected memory cell of electrically erasable and programmable nonvolatile memory cells of a nonvolatile semiconductor memory in response to an input datum of a particular logic level, said method comprising: a first programming step of programming said selected memory cell in response to said input datum by applying a first programming pulse to said selected memory cell to make said selected memory cell have a programmed threshold voltage; a first verifying step of verifying whether said selected memory cell has the programmed threshold voltage which is not greater than a first predetermined upper limit voltage; a re-executing step of re-executing said first programming step when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is greater than said first predetermined upper limit voltage, said re-executing step being carried out until said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said first predetermined upper limit voltage; a second verifying step of verifying, when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said first predetermined upper limit voltage, whether said selected memory cell has the programmed threshold voltage which is not greater than a second predetermined upper limit voltage less than said first predetermined upper limit voltage; a second programming step of programming, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is greater than said second predetermined upper limit voltage, said selected memory cell by applying a second programming pulse different from said first programming pulse to said selected memory cell so as to make said selected memory cell have the programmed threshold voltage which is not greater than said second predetermined upper limit voltage; and a completion step of completing programming of said selected memory cell when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said second predetermined upper limit voltage.
Claim 3
Dependent Claim
23 words
A method as claimed in claim 1, wherein the particular logic level of said input datum is other than a logic "0" level.
Claim 4
Independent Claim
464 words
A method of programming a selected memory cell of electrically erasable and programmable nonvolatile memory cells of a nonvolatile semiconductor memory in response to an input datum of a particular logic level, said method comprising: a first programming step of programming said selected memory cell in response to said input datum by applying a first programming pulse to said selected memory cell to make said selected memory cell have a programmed threshold voltage; a first verifying step of verifying whether said selected memory cell has the programmed threshold voltage which is not greater than a first predetermined upper limit voltage; a re-executing step of re-executing said first programming step when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is greater than said first predetermined upper limit voltage, said re-executing step being carried out until said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said first predetermined upper limit voltage; a second verifying step of verifying, when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said first predetermined upper limit voltage, whether said selected memory cell has the programmed threshold voltage which is not greater than a second predetermined upper limit voltage less than said first predetermined upper limit voltage; a second programming step of programming, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is greater than said second predetermined upper limit voltage, said selected memory cell by applying a second programming pulse different from said first programming pulse to said selected memory cell so as to make said selected memory cell have the programmed threshold voltage which is not greater than said second predetermined upper limit voltage; a third verifying step of verifying, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said second predetermined upper limit voltage, whether said selected memory cell has the programmed threshold voltage which is not less than a predetermined lower limit voltage less than said second predetermined upper limit voltage; and a completion step of completing programming of said selected memory cell with said selected memory cell identified as a normally programmed cell when said third verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said predetermined lower limit voltage, said completion step completing said programming of said selected memory cell with said selected memory cell identified as an abnormally programmed cell when said third verifying step verifies that said selected memory cell has the programmed threshold voltage which is less than said predetermined lower limit voltage.
Claim 5
Independent Claim
464 words
A method of programming a selected memory cell of electrically erasable and programmable nonvolatile memory cells of a nonvolatile semiconductor memory in response to an input datum of a particular logic level, said method comprising: a first programming step of programming said selected memory cell in response to said input datum by applying a first programming pulse to said selected memory cell to make said selected memory cell have a programmed threshold voltage; a first verifying step of verifying whether said selected memory cell has the programmed threshold voltage which is not greater than a first predetermined upper limit voltage; a re-executing step of re-executing said first programming step when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is greater than said first predetermined upper limit voltage, said re-executing step being carried out until said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said first predetermined upper limit voltage; a second verifying step of verifying, when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said first predetermined upper limit voltage, whether said selected memory cell has the programmed threshold voltage which is not greater than a second predetermined upper limit voltage less than said first predetermined upper limit voltage; a second programming step of programming, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is greater than said second predetermined upper limit voltage, said selected memory cell by applying a second programming pulse different from said first programming pulse to said selected memory cell so as to make said selected memory cell have the programmed threshold voltage which is not greater than said second predetermined upper limit voltage; a third verifying step of verifying, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said second predetermined upper limit voltage, whether said selected memory cell has the programmed threshold voltage which is not less than a predetermined lower limit voltage less than said second predetermined upper limit voltage; and a completion step of completing programming of said selected memory cell with said selected memory cell identified as a normally programmed cell when said third verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said predetermined lower limit voltage, said completion step completing said programming of said selected memory cell with said selected memory cell identified as an abnormally programmed cell when said third verifying step verifies that said selected memory cell has the programmed threshold voltage which is less than said predetermined lower limit voltage.
Claim 6
Dependent Claim
23 words
A method as claimed in claim 3, wherein the particular logic level of said input datum is other than a logic "0" level.
Claim 7
Independent Claim
346 words
A method of programming a selected memory cell of electrically erasable and programmable nonvolatile memory cells of a nonvolatile semiconductor memory in response to an input datum of a particular logic level, said method comprising: a first programming step of programming said selected memory cell in response to said input datum by applying a first programming pulse to said selected memory cell to make said selected memory cell have a programmed threshold voltage; a first verifying step of verifying whether said selected memory cell has the programmed threshold voltage which is not less than a first predetermined lower limit voltage; a re-executing step of re-executing said first programming step when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is less than said first predetermined lower limit voltage, said re-executing step being carried out until said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said first predetermined lower limit voltage; a second verifying step of verifying, when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said first predetermined lower limit voltage, whether said selected memory cell has the programmed threshold voltage which is not less than a second predetermined lower limit voltage greater than said first predetermined lower limit voltage; a second programming step of programming, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is less than said second predetermined lower limit voltage, said selected memory cell by applying a second programming pulse different from said first programming pulse to said selected memory cell so as to make said selected memory cell have the programmed threshold voltage which is not less than said second predetermined lower limit voltage; and a completion step of completing programming of said selected memory cell when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said second predetermined lower limit voltage.
Claim 8
Independent Claim
346 words
A method of programming a selected memory cell of electrically erasable and programmable nonvolatile memory cells of a nonvolatile semiconductor memory in response to an input datum of a particular logic level, said method comprising: a first programming step of programming said selected memory cell in response to said input datum by applying a first programming pulse to said selected memory cell to make said selected memory cell have a programmed threshold voltage; a first verifying step of verifying whether said selected memory cell has the programmed threshold voltage which is not less than a first predetermined lower limit voltage; a re-executing step of re-executing said first programming step when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is less than said first predetermined lower limit voltage, said re-executing step being carried out until said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said first predetermined lower limit voltage; a second verifying step of verifying, when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said first predetermined lower limit voltage, whether said selected memory cell has the programmed threshold voltage which is not less than a second predetermined lower limit voltage greater than said first predetermined lower limit voltage; a second programming step of programming, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is less than said second predetermined lower limit voltage, said selected memory cell by applying a second programming pulse different from said first programming pulse to said selected memory cell so as to make said selected memory cell have the programmed threshold voltage which is not less than said second predetermined lower limit voltage; and a completion step of completing programming of said selected memory cell when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said second predetermined lower limit voltage.
Claim 9
Dependent Claim
23 words
A method as claimed in claim 5, wherein the particular logic level of said input datum is other than a logic "0" level.
Claim 10
Independent Claim
464 words
A method of programming a selected memory cell of electrically erasable and programmable nonvolatile memory cells of a nonvolatile semiconductor memory in response to an input datum of a particular logic level, said method comprising: a first programming step of programming said selected memory cell in response to said input datum by applying a first programming pulse to said selected memory cell to make said selected memory cell have a programmed threshold voltage; a first verifying step of verifying whether said selected memory cell has the programmed threshold voltage which is not less than a first predetermined lower limit voltage; a re-executing step of re-executing said first programming step when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is less than said first predetermined lower limit voltage, said re-executing step being carried out until said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said first predetermined lower limit voltage; a second verifying step of verifying, when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said first predetermined lower limit voltage, whether said selected memory cell has the programmed threshold voltage which is not less than a second predetermined lower limit voltage greater than said first predetermined lower limit voltage; a second programming step of programming, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is less than said second predetermined lower limit voltage, said selected memory cell by applying a second programming pulse different from said first programming pulse to said selected memory cell so as to make said selected memory cell have the programmed threshold voltage which is not less than said second predetermined lower limit voltage; a third verifying step of verifying, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said second predetermined lower limit voltage, whether said selected memory cell has the programmed threshold voltage which is not greater than a predetermined upper limit voltage greater than said second predetermined lower limit voltage; and a completion step of completing programming of said selected memory cell with said selected memory cell identified as a normally programmed cell when said third verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said predetermined upper limit voltage, said completion step completing said programming of said selected memory cell with said selected memory cell identified as an abnormally programmed cell when said third verifying step verifies that said selected memory cell has the programmed threshold voltage which is greater than said predetermined upper limit voltage.
Claim 11
Independent Claim
464 words
A method of programming a selected memory cell of electrically erasable and programmable nonvolatile memory cells of a nonvolatile semiconductor memory in response to an input datum of a particular logic level, said method comprising: a first programming step of programming said selected memory cell in response to said input datum by applying a first programming pulse to said selected memory cell to make said selected memory cell have a programmed threshold voltage; a first verifying step of verifying whether said selected memory cell has the programmed threshold voltage which is not less than a first predetermined lower limit voltage; a re-executing step of re-executing said first programming step when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is less than said first predetermined lower limit voltage, said re-executing step being carried out until said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said first predetermined lower limit voltage; a second verifying step of verifying, when said first verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said first predetermined lower limit voltage, whether said selected memory cell has the programmed threshold voltage which is not less than a second predetermined lower limit voltage greater than said first predetermined lower limit voltage; a second programming step of programming, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is less than said second predetermined lower limit voltage, said selected memory cell by applying a second programming pulse different from said first programming pulse to said selected memory cell so as to make said selected memory cell have the programmed threshold voltage which is not less than said second predetermined lower limit voltage; a third verifying step of verifying, when said second verifying step verifies that said selected memory cell has the programmed threshold voltage which is not less than said second predetermined lower limit voltage, whether said selected memory cell has the programmed threshold voltage which is not greater than a predetermined upper limit voltage greater than said second predetermined lower limit voltage; and a completion step of completing programming of said selected memory cell with said selected memory cell identified as a normally programmed cell when said third verifying step verifies that said selected memory cell has the programmed threshold voltage which is not greater than said predetermined upper limit voltage, said completion step completing said programming of said selected memory cell with said selected memory cell identified as an abnormally programmed cell when said third verifying step verifies that said selected memory cell has the programmed threshold voltage which is greater than said predetermined upper limit voltage.
Claim 12
Dependent Claim
23 words
A method as claimed in claim 7, wherein the particular logic level of said input datum is other than a logic "0" level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-25 | 2001-11-24 | 2002-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-25 | 2005-11-24 | 2006-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-25 | 2009-11-24 | 2010-05-26 | $7700.00 | Window Closed / Lapsed |