US5778200A
Expired / Lapsed
US
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Bus arbiter including aging factor counters to dynamically vary arbitration priority
Assignee: GlobalFoundries Inc
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Filing: 1995-11-21
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Granted: 1998-07-07
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Expires: 2015-11-21
Abstract
Abstract A computer system for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of counters referred to as "aging factor" counters is further provided wherein a separate counter unit corresponds to each bus master. Each counter is configured to generate a signal indicative of a lapse of time since a time when the peripheral was last granted ownership of the bus. An arbitration control unit is coupled to the aging factor counters, the request detection unit and the grant generator for processing incoming bus request signals. The arbitration control unit is configured to dynamically vary the level of arbitration priority given to each peripheral device based upon the aging signal corresponding to the device. Accordingly, as a greater period of time elapses when a peripheral device last owned the bus, the greater the level of arbitration priority that is given to a bus request by that peripheral. A set of programmable registers are provided to allow software programming of the initial count value associated with each aging counter. The aging counter for a particular device may further be held or inhibited from counting to provide a constant level of priority for that particular peripheral device.
Inventors
- 👤 Dale E. Gulick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:09
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364; G06F13/3625
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
153 words
A bus arbiter for controlling and prioritizing ownership of a bus comprising: a request detection unit for detecting a plurality of bus request signals corresponding to designated bus masters; a grant generator for generating a plurality of bus grant signals; an arbitration control unit coupled to said request detection unit and to said grant generator, wherein said arbitration control unit is configured to process contending bus requests received by said request detection unit; and a first counter unit coupled to said arbitration control unit wherein said first counter unit is configured to generate a first aging signal indicative of a first lapse of time following a termination of mastership of said bus to a designated peripheral device; wherein said arbitration control unit is further configured to increase a level of arbitration priority given to said designated peripheral device in response to said aging signal indicating an increase in said first lapse of time.
Claim 2
Dependent Claim
153 words
A bus arbiter for controlling and prioritizing ownership of a bus comprising: a request detection unit for detecting a plurality of bus request signals corresponding to designated bus masters; a grant generator for generating a plurality of bus grant signals; an arbitration control unit coupled to said request detection unit and to said grant generator, wherein said arbitration control unit is configured to process contending bus requests received by said request detection unit; and a first counter unit coupled to said arbitration control unit wherein said first counter unit is configured to generate a first aging signal indicative of a first lapse of time following a termination of mastership of said bus to a designated peripheral device; wherein said arbitration control unit is further configured to increase a level of arbitration priority given to said designated peripheral device in response to said aging signal indicating an increase in said first lapse of time.
Claim 3
Dependent Claim
53 words
The bus arbiter as recited in claim 1 further comprising a second counter unit coupled to said arbitration control unit wherein said second counter unit is configured to generate a second aging signal indicative of a second lapse of time following a termination of mastership of said bus to a second peripheral device.
Claim 4
Dependent Claim
44 words
The bus arbiter as recited in claim 2 wherein said arbitration control unit is configured to increase a level of arbitration priority given to said second peripheral device in response to said second aging signal indicating an increase in said second lapse of time.
Claim 5
Dependent Claim
38 words
The bus arbiter as recited in claim 3 further comprising a programmable storage unit configured to store a first initial count value for said first counter unit and a second initial count value for said second counter unit.
Claim 6
Dependent Claim
18 words
The bus arbiter as recited in claim 4 wherein said programmable storage unit includes a plurality of registers.
Claim 7
Dependent Claim
28 words
The bus arbiter as recited in claim 4 wherein said programmable storage unit is further configured to store a bit to inhibit said first counter unit from counting.
Claim 8
Dependent Claim
33 words
The bus arbiter as recited in claim 5 wherein each of said plurality of said registers is configured to store a parameter that controls whether an associated counter unit is inhibited from counting.
Claim 9
Dependent Claim
45 words
The bus arbiter as recited in claim 4 further comprising a decoder coupled to said programmable storage unit, wherein said decoder is configured to decode an address signal to thereby allow a setting of said first initial count value stored within said programmable storage unit.
Claim 10
Dependent Claim
252 words
A computer system comprising: a microprocessor; a bus bridge coupled to said microprocessor through a CPU local bus; an expansion bus coupled to said bus bridge, wherein said bus bridge is configured to accommodate data transfers between said CPU local bus and said expansion bus; a real time master coupled to said expansion bus, wherein said real time master is configured to perform real time processing functions; a non-real time master coupled to said expansion bus, wherein said non-real time master is configured to perform non-real time processing functions; and a bus arbiter for controlling and prioritizing ownership of said expansion bus including: a request detection unit for detecting a first request signal of said real time master and a second request signal of said non-real time master; a grant generator for generating a plurality of bus grant signals; an arbitration control unit coupled to said request detection unit and to said grant generator, wherein said arbitration control unit is configured to process contending bus requests received by said request detection unit; and a first counter unit coupled to said arbitration control unit wherein said first counter unit is configured to generate a first aging signal indicative of a first lapse of time following a termination of mastership of said expansion bus to real time master; wherein said arbitration control unit is further configured to increase a level of arbitration priority given to said real time master in response to said aging signal indicating an increase in said first lapse of time.
Claim 11
Dependent Claim
252 words
A computer system comprising: a microprocessor; a bus bridge coupled to said microprocessor through a CPU local bus; an expansion bus coupled to said bus bridge, wherein said bus bridge is configured to accommodate data transfers between said CPU local bus and said expansion bus; a real time master coupled to said expansion bus, wherein said real time master is configured to perform real time processing functions; a non-real time master coupled to said expansion bus, wherein said non-real time master is configured to perform non-real time processing functions; and a bus arbiter for controlling and prioritizing ownership of said expansion bus including: a request detection unit for detecting a first request signal of said real time master and a second request signal of said non-real time master; a grant generator for generating a plurality of bus grant signals; an arbitration control unit coupled to said request detection unit and to said grant generator, wherein said arbitration control unit is configured to process contending bus requests received by said request detection unit; and a first counter unit coupled to said arbitration control unit wherein said first counter unit is configured to generate a first aging signal indicative of a first lapse of time following a termination of mastership of said expansion bus to real time master; wherein said arbitration control unit is further configured to increase a level of arbitration priority given to said real time master in response to said aging signal indicating an increase in said first lapse of time.
Claim 12
Dependent Claim
49 words
The computer system as recited in claim 9, wherein said real time master is configured to assert a first request signal to request ownership of said expansion bus and wherein said non-real time master is configured to assert a second request signal to request ownership of said expansion bus.
Claim 13
Dependent Claim
16 words
The computer system as recited in claim 9 wherein said expansion bus is a PCI bus.
Claim 14
Dependent Claim
17 words
The computer system as recited in claim 9 wherein said real time master is an audio adapter.
Claim 15
Dependent Claim
54 words
The computer system as recited in claim 9 further comprising a second counter unit coupled to said arbitration control unit wherein said second counter unit is configured to generate a second aging signal indicative of a second lapse of time following a termination of mastership of said expansion bus to said non-real time master.
Claim 16
Dependent Claim
44 words
The computer system as recited in claim 13 wherein said arbitration control unit is configured to increase a level of arbitration priority given to said non-real time master in response to said second aging signal indicating an increase in said second lapse of time.
Claim 17
Dependent Claim
38 words
The computer system as recited in claim 14 further comprising a programmable storage unit configured to store a first initial count value for said first counter unit and a second initial count value for said second counter unit.
Claim 18
Dependent Claim
18 words
The computer system as recited in claim 15 wherein said programmable storage unit includes a plurality of registers.
Claim 19
Dependent Claim
28 words
The computer system as recited in claim 15 wherein said programmable storage unit is further configured to store a bit to inhibit said first counter unit from counting.
Claim 20
Dependent Claim
33 words
The computer system as recited in claim 16 wherein each of said plurality of said registers is configured to store a parameter that controls whether an associated counter unit is inhibited from counting.
Claim 21
Dependent Claim
45 words
The computer system as recited in claim 15 further comprising a decoder coupled to said programmable storage unit, wherein said decoder is configured to decode an address signal to thereby allow a setting of said first initial count value stored within said programmable storage unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |