Pre-arbitration system allowing look-around and bypass for significant operations

Claim 3

A bus access arbitration system in a computer network for modifying the priority sequence of bus access according to the types of Read/Write or Non-Read/Write commands residing in FIFO register queues, said system comprising: (a) bus means for carrying Write Commands, Read Commands, and Non-Read/Non-Write commands from a first digital module to a second digital module; (b) bus arbitration means for receiving bus request for access from said first digital module; (c) Queue means for holding incompleted Write, Read, and Non-Read/Non-Write Commands which are normally given bus access on a first-in-first-out sequential order; (d) Pre-arbitration means for modifying the said first-in-first-out sequential order to alter the sequence of bus access, said means including: (d1) look-around means to compare the Read-address of a later-received Read command with the Write-address of any earlier-received Write commands; (d2) system bus sequential control means to modify the first-in-first-out sequence of commands so that said later-received Read command is placed ahead in sequence for bus access of said earlier received Write commands, when said look-around means signals a "no-match" in said Read-address value and said Write address value, said sequential control means deferring bus access for said Non-Read/Non-Write commands until after the execution of said Read/Write commands residing in said queue means.

Claim 4

A bus access arbitration system in a computer network for modifying the priority sequence of bus access according to the types of Read/Write or Non-Read/Write commands residing in FIFO register queues, said system comprising: (a) bus means for carrying Write Commands, Read Commands, and Non-Read/Non-Write commands from a first digital module to a second digital module; (b) bus arbitration means for receiving bus request for access from said first digital module; (c) Queue means for holding incompleted Write, Read, and Non-Read/Non-Write Commands which are normally given bus access on a first-in-first-out sequential order; (d) Pre-arbitration means for modifying the said first-in-first-out sequential order to alter the sequence of bus access, said means including: (d1) look-around means to compare the Read-address of a later-received Read command with the Write-address of any earlier-received Write commands; (d2) system bus sequential control means to modify the first-in-first-out sequence of commands so that said later-received Read command is placed ahead in sequence for bus access of said earlier received Write commands, when said look-around means signals a "no-match" in said Read-address value and said Write address value, said sequential control means deferring bus access for said Non-Read/Non-Write commands until after the execution of said Read/Write commands residing in said queue means.

Claim 5

In a computer network wherein a central processing module having a processor, a control PAL and data path array having queue means for holding pending incomplete processor commands, said data path array interfacing to dual system busses which connect to an external main memory and an input/output module, a system for modifying the priority of access to said dual system busses for processor commands from a sequential time sequence to a modified order of priority in order to increase throughput, said system comprising: (a) means to normally execute Read OPs, Write OPs, Time of Day OPs, Send Message OPs and Read-Lock OPs in the order of the time sequence that each OP occurred by granting bus access for each OP at the time of occurrence of said OP; (b) means to modify the priority of bus access so that a Read OP occurring after a Write OP will be given bus access priority as long as the Read OP has a different address from said Write OP, said means to modify including: (b1) means to defer bus access for Send Message OPs, Read-Time of Day OPs, and Read-Lock OPs until said Read OPs and Write OPs have been executed and are no longer pending.

Claim 6

In a computer network wherein a central processing module having a processor, a control PAL and data path array having queue means for holding pending incomplete processor commands, said data path array interfacing to dual system busses which connect to an external main memory and an input/output module, a system for modifying the priority of access to said dual system busses for processor commands from a sequential time sequence to a modified order of priority in order to increase throughput, said system comprising: (a) means to normally execute Read OPs, Write OPs, Time of Day OPs, Send Message OPs and Read-Lock OPs in the order of the time sequence that each OP occurred by granting bus access for each OP at the time of occurrence of said OP; (b) means to modify the priority of bus access so that a Read OP occurring after a Write OP will be given bus access priority as long as the Read OP has a different address from said Write OP, said means to modify including: (b1) means to defer bus access for Send Message OPs, Read-Time of Day OPs, and Read-Lock OPs until said Read OPs and Write OPs have been executed and are no longer pending.

Claim 7

The system of claim 3 wherein said means to modify priority includes: (i) control PAL means connected to a system bus arbitration logic means which grants bus access, and including: (ia) pre-arbitration logic means connected to said processor and to a system bus sequence control means for determining a modified order of bus access other than a straight time sequence of bus access according to the time of origin of a processor command, said modified order of bus access setting a priority of access for pending Reads before pending Writes but deferring bus access for non-Write and non-Read commands; (ii) said system bus arbitration means for receiving bus access requests and for granting bus access under control of said system bus sequence control means; (iii) queue means for holding pending non-executed Read, Write, Read-Lock, Time of Day, and Send-Message OPs until selected by said pre-arbitration logic for access to a system bus.