Voltage booster circuit

Claim 2

A voltage booster circuit having a charge transfer circuit wherein charges are transferred from a lowest node to a highest node, comprising: switching means for selecting one of a positive high voltage output mode and a negative high voltage output mode, a positive high voltage being output from said highest node by supplying a first power supply voltage to said lowest node in said positive high voltage output mode, and a negative high voltage being output from said lowest node by supplying a second power supply voltage to said highest node in said negative high voltage output mode.

Claim 3

A voltage booster circuit recited in claim 1, wherein: said lowest node is connected to said first power supply voltage through a first switch; said highest node is connected to said second power supply voltage through a second switch; said first switch is turned to ON and said second switch is turned to OFF in said positive high voltage output mode; and said first switch is turned to OFF and said second switch is turned to ON in said negative high voltage output mode.

Claim 4

A voltage booster circuit recited in claim 2, wherein: potential of said first power supply voltage is equal to potential of a power supply terminal of an IC chip where the voltage booster circuit is provided; and potential of said second power supply voltage is equal to potential of a ground terminal of said IC chip.

Claim 5

A voltage booster circuit recited in claim 1, wherein: amplitude of complementary clock signals supplied to said charge transfer circuit in said positive high voltage output mode is controlled to be different to amplitude of said complementary signals in said negative high voltage output mode.

Claim 6

A voltage booster circuit recited in claim 1, wherein: frequency of complementary clock signals supplied to said charge transfer circuit in said positive high voltage output mode is controlled to be different to frequency of said complementary clock signals in said negative high voltage output mode.

Claim 7

A voltage booster circuit recited in claim 4, comprising a changeover circuit for selecting said complementary clock signals to be supplied to said charge transfer circuit from more than one pair of complementary clock signals having different amplitude.

Claim 8

A voltage booster circuit recited in claim 5, comprising a changeover circuit for selecting said complementary clock signals to be supplied to said charge transfer circuit from more than one pair of complementary clock signals having different frequency.

Claim 9

A voltage booster circuit recited in claim 1, wherein said charge transfer circuit supplied with a pair of complementary clock signals comprises a cascade connection of a plurality of pumping units: a first of said plurality of pumping units having a node supplied from said lowest node through a diode connection of a MOS transistor and coupled to one of said pair of complementary clock signals through a capacitor; and other each of said plurality of pumping units having a node coupled through a capacitor to one of said pair of complementary clock signals and supplied from a node of a preceding pumping unit of said other each of said plurality pumping units through a diode connection of MOS transistor, said node of said preceding pumping unit coupled to the other of said pair of complementary clock signals through another capacitor.

Claim 10

A voltage booster circuit recited in claim 1, wherein said charge transfer circuit comprises a cascade connection of a plurality of pumping units supplied with two pairs of complementary clock signals of the same frequency: each of said two pairs of clock signals being a pair of a narrow pulse signal and a wide pulse signal having the same phase, π different with each other pair; a first of said plurality of pumping units having a node supplied from said lowest node through a MOS transistor with its gate bootstrapped coupled through a capacitor to said narrow pulse signal of one of said two pairs of clock signals and diode-connected through another MOS transistor gated by potential of said node coupled through another capacitor to said wide pulse signal of said one of said two pairs of clock signals; and other each of said plurality of pumping units having a node supplied from a node of a preceding pumping unit of said other each of said plurality pumping units through a MOS transistor with its gate bootstrapped coupled through a capacitor to said narrow pulse signal of one of said two pairs of clock signals and diode-connected through another MOS transistor gated by potential of said node coupled through another capacitor to said wide pulse signal of said one of said two pairs of clock signals, said node of said preceding pumping unit coupled through a capacitor to said wide pulse signal of the other of said two pairs of clock signals.