Memory system having multiple programmable reference cells

Claim 1

A memory comprising: a storage array containing rows and columns of storage cells, wherein each storage cell is electrically programmable to represent a stored value, each storage cell comprising a floating gate transistor having threshold voltage indicating the value stored in the storage cell; a reference array containing rows and columns reference cells, wherein each row of reference cells contains a plurality of reference cells that are electrically programmable and programmed to represent different reference values, each reference cell comprising a floating gate transistor having a threshold voltage, the threshold voltage of the reference cell indicating the reference value of the reference cell; a plurality of row lines, wherein each row line is associated with and connects together storage cells in a row in the storage array and reference cells in a row in the reference array; and a write circuit operably coupled to select a storage cell, select a first reference cell that was programmed to represent a first reference value corresponding to a data value being written, and change the threshold voltage of the selected storage cell in response to a feedback signal from the selected storage cell differing from a first reference signal from the first reference cell, wherein: in response to a data input signal representing the data value being written, the write circuit causes the first reference cell and a second reference cell to respectively generate the first reference signal and a second reference signal, the second reference cell being preprogrammed to represent a second reference value corresponding to a data value being written; and when changing the state of the selected storage cell, the write circuit increases the threshold voltage of the selected storage cell in response to a difference between the feedback signal and the first reference signal indicating that the first reference cell has a threshold voltage higher than that of the selected storage cell and decreases the threshold voltage of the selected storage cell in response to a difference between the feedback signal and the second reference signal indicating that the second reference cell has a threshold voltage lower than that of the selected storage cell.

Claim 4

A method for writing a data value into a selected storage cell in a memory array, comprising: electrically programming reference cells in the memory array, wherein each row of the array includes a plurality of reference cells that are programmed to represent different reference values; activating a row line that is connected to the selected storage cell and to a plurality of reference cells in a selected row containing the selected storage cell; selecting a bit line that is coupled to the selected storage cell; selecting a first reference bit line from among bit lines coupled to the reference cells in the selected row, wherein the first reference bit line is selected according to the data value being written; and changing a state of the selected storage cell in response to a first difference between a first reference signal on the first reference bit line and a feedback signal on the bit line coupled to the selected storage cell; selecting a second reference bit line from among the bit lines coupled to the reference cells in the selected row, wherein the second reference bit line is selected according to the data value being written; and changing the state of the selected storage cell in response to a second difference between the feedback signal and a second reference signal on the second reference bit line.

Claim 5

A method for writing a data value into a selected storage cell in a memory array, comprising: electrically programming reference cells in the memory array, wherein each row of the array includes a plurality of reference cells that are programmed to represent different reference values; activating a row line that is connected to the selected storage cell and to a plurality of reference cells in a selected row containing the selected storage cell; selecting a bit line that is coupled to the selected storage cell; selecting a first reference bit line from among bit lines coupled to the reference cells in the selected row, wherein the first reference bit line is selected according to the data value being written; and changing a state of the selected storage cell in response to a first difference between a first reference signal on the first reference bit line and a feedback signal on the bit line coupled to the selected storage cell; selecting a second reference bit line from among the bit lines coupled to the reference cells in the selected row, wherein the second reference bit line is selected according to the data value being written; and changing the state of the selected storage cell in response to a second difference between the feedback signal and a second reference signal on the second reference bit line.