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Patent US5848010A successfully refreshed from Google Patents.
US5848010A
Expired / Lapsed
US
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Circuit and method for antifuse stress test
Assignee: Micron Technology Inc
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Filing: 1997-07-14
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Granted: 1998-12-08
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Expires: 2017-07-14
Abstract
Abstract A test circuit for stress testing antifuses before programming. The test circuit provides a voltage to an antifuse detection circuit during antifuse stress testing. In one embodiment, the provided voltage is externally received at a probe pad. In another embodiment, the test circuit controls a voltage generating circuit output voltage from a normal operating voltage to a stress voltage, such as by shifting the ground reference for the voltage generating circuit. The stress voltage can be varied as needed for a particular test setup and/or for different batches of antifuse circuits. Since the stress voltage is independent of the power supply voltage VCC, antifuse stressing can be concurrent with other pre-fuse tests, obviating the need for a dedicated antifuse stress test and reducing test time.
Inventors
- 👤 Joseph C. Sher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:06
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; G11C29/00; G11C29/02
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
83 words
A test circuit for providing to a test element an operating voltage, in a normal mode of operation, and a stress voltage, in an stress test mode of operation, the test circuit comprising: an output node coupled to the test element; a first gating circuit for coupling the output of a voltage source to the output node; a second gating circuit for coupling a stress voltage received from an external pad to the output node in response to a stress voltage enable signal.
Claim 2
Dependent Claim
83 words
A test circuit for providing to a test element an operating voltage, in a normal mode of operation, and a stress voltage, in an stress test mode of operation, the test circuit comprising: an output node coupled to the test element; a first gating circuit for coupling the output of a voltage source to the output node; a second gating circuit for coupling a stress voltage received from an external pad to the output node in response to a stress voltage enable signal.
Claim 3
Dependent Claim
19 words
The test circuit of claim 1, wherein the output node is coupled to the test element through a transistor.
Claim 4
Dependent Claim
32 words
The test circuit of claim 2, wherein a gate terminal of the transistor is coupled to the output node and a source/drain terminal of the transistor is coupled to the test element.
Claim 5
Dependent Claim
40 words
The test circuit of claim 1, wherein the stress voltage is applied to an antifuse test element through the control input of a pass gate for regulating the voltage that is applied to the antifuse by an antifuse detection circuit.
Claim 6
Dependent Claim
80 words
A test circuit for providing to a test element, an operating voltage, in a normal mode of operation, and a stress voltage, in a stress test mode of operation, the test circuit comprising: an output node coupled to the test element; a voltage generating circuit for providing an output voltage to the output node; and a control circuit, responsive to a stress voltage enable signal, for adjusting the output voltage from the operating voltage level to the stress voltage level.
Claim 7
Dependent Claim
80 words
A test circuit for providing to a test element, an operating voltage, in a normal mode of operation, and a stress voltage, in a stress test mode of operation, the test circuit comprising: an output node coupled to the test element; a voltage generating circuit for providing an output voltage to the output node; and a control circuit, responsive to a stress voltage enable signal, for adjusting the output voltage from the operating voltage level to the stress voltage level.
Claim 8
Dependent Claim
19 words
The test circuit of claim 5, wherein the output node is coupled to the test element through a transistor.
Claim 9
Dependent Claim
32 words
The test circuit of claim 6, wherein a gate terminal of the transistor is coupled to the output node and a source/drain terminal of the transistor is coupled to the test element.
Claim 10
Dependent Claim
40 words
The test circuit of claim 5, wherein the stress voltage is applied to an antifuse test element through the control input of a pass gate for regulating the voltage that is applied to the antifuse by an antifuse detection circuit.
Claim 11
Dependent Claim
32 words
The test circuit of claim 5, including a reference shifting circuit for changing a ground reference of the voltage generating circuit, thereby shifting the level of the output voltage relative to ground.
Claim 12
Dependent Claim
46 words
The test circuit of claim 5, wherein the reference shifting circuit includes a bias circuit interposed between the voltage generating circuit and ground, and a shunt circuit, in parallel with the bias circuit, for shunting the bias circuit, thereby coupling the voltage generating circuit to ground.
Claim 13
Dependent Claim
35 words
The test circuit of claim 10, wherein the shunt and bias circuits increase the output voltage from the operating voltage level to the stress test voltage level in response to a stress voltage enable signal.
Claim 14
Dependent Claim
103 words
A semiconductor memory device, comprising: a memory array having a plurality of addressable memory cells; an addressing circuit for accessing the memory cells; a plurality of programmable elements associated with the addressing circuit, having a detection circuit for detecting the element's programming state; and a test circuit for stress testing the element, the test circuit comprising: an output node coupled to the element; a voltage generating circuit providing an output voltage to the output node; and a control circuit for controlling the output voltage at the output node between an operating voltage and a stress voltage, based upon a stress voltage enable signal.
Claim 15
Dependent Claim
103 words
A semiconductor memory device, comprising: a memory array having a plurality of addressable memory cells; an addressing circuit for accessing the memory cells; a plurality of programmable elements associated with the addressing circuit, having a detection circuit for detecting the element's programming state; and a test circuit for stress testing the element, the test circuit comprising: an output node coupled to the element; a voltage generating circuit providing an output voltage to the output node; and a control circuit for controlling the output voltage at the output node between an operating voltage and a stress voltage, based upon a stress voltage enable signal.
Claim 16
Dependent Claim
12 words
The memory device of claim 12, wherein the programmable elements are antifuses.
Claim 17
Dependent Claim
18 words
The memory device of claim 12, wherein the memory array is a dynamic random access memory (DRAM) array.
Claim 18
Dependent Claim
18 words
The memory device of claim 12, wherein the output node is coupled to the element through a transistor.
Claim 19
Dependent Claim
31 words
The test circuit of claim 15, wherein a gate terminal of the transistor is coupled to the output node and a source/drain terminal of the transistor is coupled to the element.
Claim 20
Dependent Claim
40 words
The test circuit of claim 12, wherein the stress voltage is applied to an antifuse programmable element through the control input of a pass gate for regulating the voltage that is applied to the antifuse by an antifuse detection circuit.
Claim 21
Independent Claim
41 words
A method for stress testing a test element, the method comprising: decoupling, from a voltage generating circuit, an output node coupled to the test element; coupling the output node to a probe pad; and applying a stress voltage to the pad.
Claim 22
Independent Claim
41 words
A method for stress testing a test element, the method comprising: decoupling, from a voltage generating circuit, an output node coupled to the test element; coupling the output node to a probe pad; and applying a stress voltage to the pad.
Claim 23
Dependent Claim
29 words
The method of claim 18, including adjusting the stress voltage to regulate, through a control gate of a transistor, the magnitude of a voltage applied to the test element.
Claim 24
Dependent Claim
12 words
The method of claim 18, wherein the test element is an antifuse.
Claim 25
Independent Claim
67 words
A method for stress testing a test element, the method comprising: coupling an output node to the test element; coupling a voltage generating circuit output node to the output node; adjusting the voltage generating circuit output node voltage magnitude from an operating voltage to a stress voltage; and applying the stress voltage to the output node for adjusting a voltage that is applied to the test element.
Claim 26
Independent Claim
67 words
A method for stress testing a test element, the method comprising: coupling an output node to the test element; coupling a voltage generating circuit output node to the output node; adjusting the voltage generating circuit output node voltage magnitude from an operating voltage to a stress voltage; and applying the stress voltage to the output node for adjusting a voltage that is applied to the test element.
Claim 27
Dependent Claim
29 words
The method of claim 21, including adjusting the stress voltage to regulate, through a control gate of a transistor, the magnitude of a voltage applied to the test element.
Claim 28
Dependent Claim
12 words
The method of claim 21, wherein the test element is an antifuse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |