US5859776A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for the design of a circuit
Assignee: Sony Corp
•
Filing: 1996-08-12
•
Granted: 1999-01-12
•
Expires: 2016-08-12
Abstract
Abstract In automated design, a useful insertion of a delay buffer or an increase in the delay time of the critical path could not been prevented. When inserting a logic element between two certain points on the circuit, substitution of other paths passing through the relevant insertion position is considered and the insertion position of the logic element is determined finally.
Inventors
- 👤 Kenichi Sato
- 👤 Norihisa Shirota
- 👤 Yasuhiro Iida
- 👤 Mitsuru Sasano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:04
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
102 words
A method for the design of a circuit for a logic design, comprising the steps of: receiving circuit information concerning a circuit to be designed; receiving hold time violation path information concerning paths on said circuit having a hold time greater than a predetermined time; and determining an insertion position where a logic element is inserted between certain two points on said circuit on the basis of said circuit information and said hold time violation path information, wherein said determining step determines said insertion position by taking into consideration a delay of other paths through the insertion position of said logic element.
Claim 2
Independent Claim
102 words
A method for the design of a circuit for a logic design, comprising the steps of: receiving circuit information concerning a circuit to be designed; receiving hold time violation path information concerning paths on said circuit having a hold time greater than a predetermined time; and determining an insertion position where a logic element is inserted between certain two points on said circuit on the basis of said circuit information and said hold time violation path information, wherein said determining step determines said insertion position by taking into consideration a delay of other paths through the insertion position of said logic element.
Claim 3
Dependent Claim
24 words
The method for the design of a circuit according to claim 1, wherein other paths through said inserting position are paths between storage elements.
Claim 4
Dependent Claim
28 words
The method for the design of a circuit according to claim 1, wherein said logic element is an element whose output is logically not different from the input.
Claim 5
Dependent Claim
20 words
The method for the design of a circuit according to claim 3, wherein said logic element is a non-inversional buffer.
Claim 6
Dependent Claim
24 words
The method for the design of a circuit according to claim 3, wherein even numbers of inversional buffers are employed as said logic element.
Claim 7
Dependent Claim
19 words
The method for the design of a circuit according to claim 1, wherein said circuit is represented using characters.
Claim 8
Dependent Claim
19 words
The method for the design of a circuit according to claim 1, wherein said circuit is represented using drawings.
Claim 9
Dependent Claim
21 words
The method for the design of a circuit according to claim 1, wherein said circuit operates with a single-phase synchronous signal.
Claim 10
Dependent Claim
21 words
The method for the design of a circuit according to claim 1, wherein said circuit operates with a multi-phase synchronous signal.
Claim 11
Independent Claim
100 words
An apparatus for the design of a circuit, comprising: means for receiving circuit information concerning a circuit to be designed; means for receiving hold time violation path information concerning paths on said circuit having a hold time greater than a predetermined time; means for determining an insertion position where logic element is inserted between certain two points on said circuit on the basis of said circuit information and said hold time violation path information; and wherein said determining means determines said insertion position by taking into consideration a delay of other paths through the insertion position of said logic element.
Claim 12
Independent Claim
100 words
An apparatus for the design of a circuit, comprising: means for receiving circuit information concerning a circuit to be designed; means for receiving hold time violation path information concerning paths on said circuit having a hold time greater than a predetermined time; means for determining an insertion position where logic element is inserted between certain two points on said circuit on the basis of said circuit information and said hold time violation path information; and wherein said determining means determines said insertion position by taking into consideration a delay of other paths through the insertion position of said logic element.
Claim 13
Dependent Claim
25 words
The apparatus for the design of a circuit according to claim 10, wherein the other paths through said insertion point are paths between storage elements.
Claim 14
Dependent Claim
28 words
The apparatus for the design of a circuit according to claim 10, wherein said logic element is an element whose output is logically not different from the input.
Claim 15
Dependent Claim
20 words
The apparatus for the design of a circuit according to claim 10, wherein said logic element is a non-inversional buffer.
Claim 16
Dependent Claim
27 words
The apparatus for the design of a circuit according to claim 10, wherein even numbers of inversional buffers are employed as said logic element to be inserted.
Claim 17
Dependent Claim
24 words
The apparatus for the design of a circuit according to claim 13, wherein the information concerning said circuit is expressed in terms of characters.
Claim 18
Dependent Claim
24 words
The apparatus for the design of a circuit according to claim 13, wherein the information concerning said circuit is expressed in terms of drawings.
Claim 19
Dependent Claim
21 words
The apparatus for the design of a circuit according to claim 13, wherein said circuit operates with a single-phase synchronous signal.
Claim 20
Dependent Claim
21 words
The apparatus for the design of a circuit according to claim 13, wherein said circuit operates with a multi-phase synchronous signal.
Claim 21
Independent Claim
188 words
A method for the design of a circuit for a logic design, comprising the steps of: receiving circuit information from a circuit to be designed to determine a delay time in each path of said circuit; summing the delay times of each path to determine a maximum delay time; receiving hold time violation path information from a path in said circuit having a hold time greater than a predetermined time; evaluating the effect of an insertion of a delay element for a plurality of input pins present on the path having a hold time greater than a predetermined time, wherein the circuit comprises a plurality of cells and each of the plurality of cells includes a plurality of input pins; selecting a delay element insertion position before one of the plurality of input pins based on the circuit information and the hold time violation path information by taking into consideration a delay of other paths through the delay element insertion position such that the delay element insertion position selected is a most efficient delay element insertion position; and inserting the delay element into the delay element insertion position.
Claim 22
Independent Claim
188 words
A method for the design of a circuit for a logic design, comprising the steps of: receiving circuit information from a circuit to be designed to determine a delay time in each path of said circuit; summing the delay times of each path to determine a maximum delay time; receiving hold time violation path information from a path in said circuit having a hold time greater than a predetermined time; evaluating the effect of an insertion of a delay element for a plurality of input pins present on the path having a hold time greater than a predetermined time, wherein the circuit comprises a plurality of cells and each of the plurality of cells includes a plurality of input pins; selecting a delay element insertion position before one of the plurality of input pins based on the circuit information and the hold time violation path information by taking into consideration a delay of other paths through the delay element insertion position such that the delay element insertion position selected is a most efficient delay element insertion position; and inserting the delay element into the delay element insertion position.
Claim 23
Dependent Claim
97 words
The method for the design of a circuit according to claim 1, wherein the step of evaluating the effect of an insertion of a delay element for a plurality of input pins present on the path having a hold time greater than a predetermined time, wherein the circuit comprises a plurality of cells and each of the plurality of cells includes a plurality of input pins comprises: calculating the effect of an insertion of a delay input for all cells and all input pins present on the path having a hold time greater than a predetermined time.
References Cited (Backward Citations)
US5557531A
Cited
US5410491A
Cited
US5416718A
Cited
US5618744A
Cited
US5638294A
Cited
US5663889A
Cited
US5638291A
Cited
US5693540A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |