Memory cells configurable as CAM or RAM in programmable logic devices

Claim 2

A programmable logic device comprising: an array of programmably interconnected logic cells suitable for use in implementing programmed logic functions; a dual mode memory block programmably coupled to the array of logic cells, the dual mode memory block including an array of dual mode memory cells, each dual mode memory cell being suitable for operating as a first type of memory in a first mode and as a second type of memory in a second mode, wherein each dual mode memory cell includes a data storage circuit for storing data, a comparison circuit for comparing data stored in the data storage circuit with requested data, a match line for indicating whether the stored data and the requested data match, and an isolation circuit for electrically decoupling the data storage circuit from the comparison circuit and match line; and a mode control switch circuit suitable for selectively enabling the dual mode memory cells to operate in either the first or second modes.

Claim 3

A programmable logic device as recited in claim 1 wherein each dual mode memory cell is suitable for operating as a content addressable memory cell in the first mode and as a random access memory cell in the second mode.

Claim 4

A programmable logic device as recited in claim 1 wherein the isolation circuit is coupled to the mode control switch circuit and is arranged to: electrically couple the comparison circuit and the match line with the data storage circuit in the first mode; and electrically decouple the comparison circuit and the match line from the data storage circuit in the second mode.

Claim 5

A programmable logic device as recited in claim 1 wherein the comparison circuit outputs a match address when the stored data and requested data match.

Claim 6

A programmable logic device as recited in claim 1 wherein the array of dual mode memory cells are arranged in a plurality of dual mode memory cell columns and rows, each dual mode memory cell column having a plurality of dual mode memory cell column data inputs, a plurality of dual mode memory cell column address inputs, and at least one dual mode memory cell column output.

Claim 7

A programmable logic device as recited in claim 5 wherein the dual mode memory block comprises: a column control unit suitable for selecting desired dual mode memory cell columns, the column control unit having a plurality of column control unit data inputs, a plurality of column control unit address inputs, and a plurality of column control unit data outputs coupled to selected dual mode memory cell column data inputs; a row control unit having a plurality of row control unit address inputs and at least one row control unit output; an input control unit arranged to, programmably couple a plurality of programmable data input lines to the column control unit data inputs, programmably couple a first plurality of programmable address input lines to the column control unit address inputs, and programmably couple a second plurality of programmable address input lines to the row control unit address inputs; and an output control unit programmably coupling the at least one dual mode memory cell column output to a plurality of output drivers.

Claim 8

A programmable logic device as recited in claim 5 wherein each dual mode memory cell further includes: a plurality of dual mode memory cell data lines coupled to the data storage circuit, the associated dual mode memory column data inputs and an associated dual mode memory cell column output; and a row line selectably coupled to a row control unit output.

Claim 9

A programmable logic device as recited in claim 6 wherein the input control unit further comprises: a comperand unit having a first plurality of comperand inputs programmably coupled to the plurality of programmable data input lines and a comperand output coupled to the plurality of column control unit data inputs, the comperand unit being used to store the requested data; a data-in unit having a plurality of data-in inputs programmably coupled to the plurality of programmable data input lines and a data-in output being coupled to the plurality of column control unit data inputs; a first address unit programmably coupled to a first plurality of programmable address lines, the first address unit having a plurality of first address outputs coupled to the plurality of column control unit address inputs; and a second address unit programmably coupled to a second plurality of programmable address lines, the second address unit having a plurality of second address outputs coupled to the row control unit address inputs.

Claim 10

A programmable logic device as recited in claim 6 wherein the output control unit further comprises: a priority encoder which receives the match address; and a plurality of output buffers having output buffer inputs coupled to the at least one content addressable memory cell column output and a plurality of outputs being programmably coupled to the plurality of output drivers.

Claim 11

A programmable logic device as recited in claim 9 wherein the priority encoder is capable of generating a sysmatch flag being indicative of the number of match addresses for the requested data.

Claim 12

A programmable logic device as recited in claim 9 wherein the priority encoder is capable of storing a plurality of match addresses.

Claim 13

An integrated circuit, comprising: an array of programmably interconnected logic cells suitable for use in implementing programmed logic functions; and a dual mode memory block programmably coupled to the array of logic cells, the dual mode memory block being arranged to function as content addressable memory in a first mode and to function as random access memory in a second mode wherein the dual mode memory block includes an array of dual mode memory cells, each dual mode memory cell being suitable for operating as a content addressable memory cell and as a static random access memory cell, wherein each dual mode memory cell includes a data storage circuit for storing data, a comparison circuit for comparing data stored in the data storage circuit with requested data, a match line for indicating whether the stored data and the requested data match, and an isolation circuit for electrically decoupling the data storage circuit from the comparison circuit and match line.

Claim 14

An integrated circuit, comprising: an array of programmably interconnected logic cells suitable for use in implementing programmed logic functions; and a dual mode memory block programmably coupled to the array of logic cells, the dual mode memory block being arranged to function as content addressable memory in a first mode and to function as random access memory in a second mode wherein the dual mode memory block includes an array of dual mode memory cells, each dual mode memory cell being suitable for operating as a content addressable memory cell and as a static random access memory cell, wherein each dual mode memory cell includes a data storage circuit for storing data, a comparison circuit for comparing data stored in the data storage circuit with requested data, a match line for indicating whether the stored data and the requested data match, and an isolation circuit for electrically decoupling the data storage circuit from the comparison circuit and match line.

Claim 15

An integrated circuit as recited in claim 12 wherein the integrated circuit is a programmable logic device.

Claim 16

An integrated circuit as recited in claim 12 further comprising a mode control switch circuit suitable for selectively enabling the dual mode memory cells to operate as either content addressable memory cells or random access memory cells by activating the isolation circuit.

Claim 17

A dual mode memory cell arranged to function as content addressable memory in a first mode and to function as random access memory in a second mode, the dual mode memory cell comprising: a data storage circuit for storing data, a comparison circuit for comparing data stored in the data storage circuit with requested data; a match line for indicating whether the stored data and the requested data match; and an isolation circuit for electrically decoupling the data storage circuit from the comparison circuit and match line in the second mode.

Claim 18

A dual mode memory cell arranged to function as content addressable memory in a first mode and to function as random access memory in a second mode, the dual mode memory cell comprising: a data storage circuit for storing data, a comparison circuit for comparing data stored in the data storage circuit with requested data; a match line for indicating whether the stored data and the requested data match; and an isolation circuit for electrically decoupling the data storage circuit from the comparison circuit and match line in the second mode.

Claim 19

A dual mode memory circuit as recited in claim 15 wherein the data storage circuit includes a first and a second output node and the comparison circuit includes a first and a second comparator circuit.

Claim 20

A dual mode memory circuit as recited in claim 16 wherein the isolation circuit includes a first isolating transistor electrically coupling the first comparator circuit of the comparison circuit and the first output node of the data storage circuit and a second isolating transistor electrically coupling the second comparator circuit of the comparison circuit and the second output node of the data storage circuit, the first and second isolating transistor each activated by way of a mode control switch circuit.