US5983017A
Expired / Lapsed
US
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Virtual monitor debugging method and apparatus
Assignee: Bell Semiconductor LLC
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Filing: 1996-11-12
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Granted: 1999-11-09
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Expires: 2016-11-12
Abstract
Abstract A virtual monitor controller includes a data storage device coupled to receive and output data; an instruction storage device coupled to receive and output instructions; a status storage device coupled to receive and output status data; and a mode storage device coupled to receive and output mode data. The virtual monitor controller is included in a debugger/monitor controller. A debugger/monitor system comprises a host system; the debugger/monitor controller; and a digital processor. Preferably, the controller is coupled between the processor and IC logic. A method of operating a virtual monitor comprises the steps of intercepting an instruction fetch from a microprocessor; downloading instructions from a host computer; and operating the microprocessor with the instructions. Preferably, the instructions are sequentially downloaded.
Inventors
- 👤 Steven R. Kemp
- 👤 Clifford A. Whitehill
- 👤 Alan D. Poeppleman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 02:10
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3656
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
85 words
A virtual monitor controller comprising: a data storage device coupled to receive and output data; an instruction storage device coupled to receive and output instructions; a status storage device coupled to receive and output status data; and a mode storage device coupled to receive and output mode data, said mode storage device configured to receive a fixed signal and a user selectable signal, and combine said signals to provide an interrupt signal which is selectively masked based on a valve of said user selectable signal.
Claim 2
Dependent Claim
85 words
A virtual monitor controller comprising: a data storage device coupled to receive and output data; an instruction storage device coupled to receive and output instructions; a status storage device coupled to receive and output status data; and a mode storage device coupled to receive and output mode data, said mode storage device configured to receive a fixed signal and a user selectable signal, and combine said signals to provide an interrupt signal which is selectively masked based on a valve of said user selectable signal.
Claim 3
Dependent Claim
17 words
The controller of claim 1 wherein the controller is coupled to a host system and a processor.
Claim 4
Dependent Claim
13 words
The controller of claim 1 wherein the controller is coupled to an interface.
Claim 5
Dependent Claim
14 words
The controller of claim 3 wherein the interface is compatible with a JTAG standard.
Claim 6
Dependent Claim
13 words
The controller of claim 1 wherein the controller is coupled to breakpoints logic.
Claim 7
Dependent Claim
53 words
A debugger/monitor system comprising: a host system; a debugger/monitor controller in communication with said host system; and a digital processor in communication with said controller, said controller configured to provide a user-selectable mask signal to said digital processor based on a user-defined signal which is received by said controller from said host system.
Claim 8
Dependent Claim
53 words
A debugger/monitor system comprising: a host system; a debugger/monitor controller in communication with said host system; and a digital processor in communication with said controller, said controller configured to provide a user-selectable mask signal to said digital processor based on a user-defined signal which is received by said controller from said host system.
Claim 9
Dependent Claim
16 words
The system of claim 6 wherein the controller is coupled between the processor and IC logic.
Claim 10
Dependent Claim
20 words
The system of claim 6 wherein the system is operable in a virtual monitor mode and a resident monitor mode.
Claim 11
Dependent Claim
17 words
The system of claim 6 further comprising an interface between the host system and the digital processor.
Claim 12
Dependent Claim
17 words
The system of claim 9 wherein the controller controls information between the interface and the digital processor.
Claim 13
Dependent Claim
12 words
The system of claim 9 wherein the interface is a JTAG interface.
Claim 14
Dependent Claim
14 words
The system of claim 6 wherein the controller is coupled to hardware breakpoints logic.
Claim 15
Independent Claim
63 words
A method of operating a virtual monitor comprising the steps of: intercepting an instruction fetch from a microprocessor; downloading an instruction from a host computer; and operating the microprocessor with the instruction, wherein said instruction includes a user maskable signal, and wherein a number of interrupts of said microprocessor are masked, and said number depends on a value of said user maskable signal.
Claim 16
Independent Claim
63 words
A method of operating a virtual monitor comprising the steps of: intercepting an instruction fetch from a microprocessor; downloading an instruction from a host computer; and operating the microprocessor with the instruction, wherein said instruction includes a user maskable signal, and wherein a number of interrupts of said microprocessor are masked, and said number depends on a value of said user maskable signal.
Claim 17
Dependent Claim
10 words
The method of claim 13 wherein the steps are repeated.
Claim 18
Dependent Claim
17 words
The method of claim 13 further comprising the step of automatically masking a plurality of the microprocessor.
Claim 19
Dependent Claim
15 words
An embedded integrated circuit comprising a debugger monitor configured to output a user maskable signal.
Claim 20
Dependent Claim
15 words
An embedded integrated circuit comprising a debugger monitor configured to output a user maskable signal.
Claim 21
Dependent Claim
17 words
The integrated circuit of claim 16 wherein the debugger circuit is coupled between a processor and memory.
Claim 22
Independent Claim
53 words
A method of virtual monitor mode debugging comprising the step of controlling a data bus of a processor during an instruction fetch by ignoring an address from the processor and providing an instruction on the data bus, and masking a selectable number of interrupts based on a value of a user maskable signal.
Claim 23
Independent Claim
53 words
A method of virtual monitor mode debugging comprising the step of controlling a data bus of a processor during an instruction fetch by ignoring an address from the processor and providing an instruction on the data bus, and masking a selectable number of interrupts based on a value of a user maskable signal.
Claim 24
Independent Claim
84 words
A method of downloading an instruction and controlling an embedded processor comprising the steps of: attempting a processor instruction fetch; deactivating a ready processor signal; setting a processor ready bit; downloading an instruction responsive to the reactivated ready processor signal; receiving a user maskable signal; masking a selectable number of interrupts of a processor based on a value of said user maskable signal; resetting the processor ready bit; reactivating the ready processor signal; and executing the instruction responsive to the reactivated ready processor signal.
Claim 25
Independent Claim
84 words
A method of downloading an instruction and controlling an embedded processor comprising the steps of: attempting a processor instruction fetch; deactivating a ready processor signal; setting a processor ready bit; downloading an instruction responsive to the reactivated ready processor signal; receiving a user maskable signal; masking a selectable number of interrupts of a processor based on a value of said user maskable signal; resetting the processor ready bit; reactivating the ready processor signal; and executing the instruction responsive to the reactivated ready processor signal.
Claim 26
Dependent Claim
10 words
The method of claim 19 wherein the steps are repeatable.
Claim 27
Dependent Claim
48 words
The method of claim 19 further comprising the steps of: setting a processor data ready bit if the result of the instruction previously executed stored data; uploading the stored data; resetting the processor data ready bit; and deactivating the ready processor signal after the stored data is read.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |