US5985698A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell
Assignee: Round Rock Research LLC
•
Filing: 1997-04-30
•
Granted: 1999-11-16
•
Expires: 2017-04-30
Abstract
Abstract A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.
Inventors
- 👤 Fernando Gonzalez
- 👤 Raymond A. Turi
- 👤 Graham R. Wolstenholme
- 👤 Charles L. Ingalls
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:26
CPC Classifications
H; H10; H10B; H10B63/00; H10B63/20
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
132 words
A method of making a multi-state material-based memory cell having first and second nodes on a substrate, said method comprising the steps of: a) forming said first node on an upper surface of said substrate; b) forming an oxide layer on said first node; c) forming a diode container by etching an opening into said oxide layer, said diode container having an inner surface extending from a top surface of said oxide layer downwardly into communication with said first node; d) forming a diode in said container proximate to at least a portion of said inner surface, said first node being disposed in contact with said diode; and e) forming a memory element between said diode and said second node of said memory cell, said memory element comprised of a multi-state material.
Claim 2
Independent Claim
132 words
A method of making a multi-state material-based memory cell having first and second nodes on a substrate, said method comprising the steps of: a) forming said first node on an upper surface of said substrate; b) forming an oxide layer on said first node; c) forming a diode container by etching an opening into said oxide layer, said diode container having an inner surface extending from a top surface of said oxide layer downwardly into communication with said first node; d) forming a diode in said container proximate to at least a portion of said inner surface, said first node being disposed in contact with said diode; and e) forming a memory element between said diode and said second node of said memory cell, said memory element comprised of a multi-state material.
Claim 3
Dependent Claim
45 words
The method of claim 1, wherein step (d) comprises the steps of: (i) forming a first layer of epitaxial silicon proximate to at least a portion of said inner surface of said container, and (ii) depositing a second layer of polysilicon on said first layer.
Claim 4
Dependent Claim
55 words
The method of claim 1, wherein step (d) comprises the steps of: (i) forming a first layer of amorphous silicon proximate to at least a portion of said inner surface of said container, and (ii) forming a second layer of silicon disposed on at least a portion of an exposed surface of said first layer.
Claim 5
Dependent Claim
45 words
The method of claim 1, wherein step (d) comprises the steps of: (i) forming a first layer of amorphous silicon proximate to at least a portion of said inner surface of said container, and (ii) forming a second layer of metal on said first layer.
Claim 6
Dependent Claim
47 words
The method of claim 1, wherein step (e) comprises the steps of: forming a lower electrode; depositing a chalcogenide layer above said lower electrode; and forming an upper electrode above said chalcogenide layer, said upper electrode being in contact with said second node of said memory cell.
Claim 7
Dependent Claim
55 words
The method of claim 1, wherein step (e) comprises the steps of: forming a lower electrode; forming a nitride layer above said lower electrode; depositing a chalcogenide layer above said lower electrode; and forming an upper electrode above said chalcogenide layer, said upper electrode being in contact with said second node of said memory cell.
Claim 8
Dependent Claim
24 words
The method of claim 1, wherein step (a) comprises the step of: implanting an N+ silicon region into said substrate on said exposed surface.
Claim 9
Dependent Claim
36 words
The method of claim 1, wherein step (a) comprises the steps of: implanting an N+ silicon region into said substrate on said exposed surface; and forming a strapping layer disposed in contact with said first node.
Claim 10
Independent Claim
113 words
A method of making a multi-state material-based memory cell having first and second nodes on a substrate, said method comprising the steps of: a) forming a diode container by etching a trench into said substrate, said diode container having an inner surface extending from a top surface of said substrate downwardly into the trench in said substrate; b) forming a diode in said container proximate to at least a portion of said inner surface, said first node of said memory cell being disposed in contact with said diode; and c) forming a memory element between said diode and said second node of said memory cell, said memory element comprised of a multi-state material.
Claim 11
Independent Claim
113 words
A method of making a multi-state material-based memory cell having first and second nodes on a substrate, said method comprising the steps of: a) forming a diode container by etching a trench into said substrate, said diode container having an inner surface extending from a top surface of said substrate downwardly into the trench in said substrate; b) forming a diode in said container proximate to at least a portion of said inner surface, said first node of said memory cell being disposed in contact with said diode; and c) forming a memory element between said diode and said second node of said memory cell, said memory element comprised of a multi-state material.
Claim 12
Dependent Claim
61 words
The method of claim 9, wherein step (a) comprises the steps of: (i) etching a trench into said substrate; (ii) substantially filling said trench with a layer of oxide; and (iii) etching openings in said oxide layer to define a container opening, said opening having two opposing sides defined by said trench and two opposing sides defined by said oxide layer.
Claim 13
Dependent Claim
32 words
The method of claim 9, comprising the step of: forming a first address line disposed in a surface of said substrate, said first address line being electrically coupled to said first node.
Claim 14
Dependent Claim
25 words
The method of claim 11, comprising the step of: forming a strapping layer, said strapping layer being disposed in contact with said first address line.
Claim 15
Dependent Claim
33 words
The method of claim 9, wherein step (b) comprises the steps of: (i) forming a first diode layer of implanted N- type silicon; (ii) forming a second diode layer of implanted P+ silicon.
Claim 16
Dependent Claim
47 words
The method of claim 13, wherein step (c) comprises the steps of: forming a lower electrode; depositing a chalcogenide layer above said lower electrode; and forming an upper electrode above said chalcogenide layer, said upper electrode being in contact with said second node of said memory cell.
Claim 17
Dependent Claim
34 words
The method of claim 14, wherein step (c) comprises the steps of: forming a nitride insulative layer prior to depositing said chalcogenide layer; and forming a nitride cap layer after depositing said chalcogenide layer.
Claim 18
Dependent Claim
164 words
The method of claim 15, wherein a pair of first and second multi-state material memory cells are made proximate to opposing sides of said container, each of said memory cells having a first node and a second node, and wherein step (b) comprises the step of: forming first and second diodes in at least a portion of respective regions of said substrate proximate to said opposing sides of said container, said first node of said first memory cell being disposed in contact with said first diode, and said first node of said second memory cell being disposed in contact with said second diode; and wherein step (c) comprises the steps of: forming a first memory element between said first diode and said second node of said first memory cell, said memory element being comprised of multi-state material; and forming a second memory element between said first node and said second node of said second memory cell, said memory element being comprised of multi-state material.
Claim 19
Dependent Claim
40 words
The method of claim 16, wherein step (b) comprises the steps of: forming first diode layers of N- type silicon by angular implantation; and forming second diode layers of P+ type silicon in said first diode layers by angular implantation.
Claim 20
Dependent Claim
29 words
The method of claim 16, wherein step (b) comprises the step of filling said container with an insulative filling layer effective to electrically isolate first and second memory cells.
Claim 21
Dependent Claim
47 words
The method of claim 18, wherein step (b) comprises the step of: forming first and second diode contacts, said first and second diode contacts being disposed in electrical contact between said first and second diodes and said first electrodes of said first and second memory elements, respectively.
References Cited (Backward Citations)
US3423646A
Cited
GB1319388A
Cited
US3796926A
Cited
US4099260A
Cited
US4115872A
Cited
US4194283A
Cited
US4227297A
Cited
US4203123A
Cited
US4174521A
Cited
US4502208A
Cited
US4272562A
Cited
US4499557A
Cited
US4458260A
Cited
US4569698A
Cited
EP0117045A2
Cited
US4677742A
Cited
JPS60109266A
Cited
US4666252A
Cited
US4876668A
Cited
US4892840A
Cited
US4757359A
Cited
US4823181A
Cited
US4876220A
Cited
US4881114A
Cited
US4809044A
Cited
US4804490A
Cited
US5144404A
Cited
US5534712A
Cited
US5166758A
Cited
US5414271A
Cited
US5296716A
Cited
US5335219A
Cited
US5341328A
Cited
US5534711A
Cited
US5177567A
Cited
US5166096A
Cited
US5359205A
Cited
US5363329A
Cited
US5510629A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |