Priority arbitration system providing low latency and guaranteed access for devices

Claim 2

A priority arbitration system for interfacing a plurality of peripheral component interconnect (PCI) agents coupled to a PCI bus such that high priority PCI agents are satisfied without starving low priority PCI agents, comprising: a PCI bus adapted to transmit data signals thereon; a high priority PCI agent coupled to said PCI bus; a low priority PCI agent coupled to said PCI bus; an arbiter coupled to said high priority PCI agent and said low priority PCI agent via said PCI bus; said arbiter granting ownership of said PCI bus to said high priority PCI agent, said high priority PCI agent becoming an interim low priority PCI agent after a grant to said high priority PCI agent, said low priority PCI agent having a higher priority than said interim low priority PCI agent, said interim low priority PCI agent reverting to said high priority PCI agent subsequent to a grant to said low priority PCI agent, said arbiter granting ownership of said PCI bus to said low priority PCI agent before granting ownership of said PCI bus to said interim low priority PCI agent such that said low priority PCI agent is not prevented from accessing said PCI bus by said high priority PCI agent, and wherein said high priority PCI agent becomes said interim low priority PCI agent, said interim low priority PCI agent being the lowest priority of a plurality of PCI agents requesting ownership of said PCI bus.

Claim 3

The system of claim 1, wherein said arbiter grants ownership of said PCI bus to said high priority PCI agent, said high priority PCI agent being the highest priority of a plurality of PCI agents requesting ownership of said PCI bus.

Claim 4

The system of claim 1, wherein said high priority PCI agent becomes said interim low priority PCI agent subsequent to starting a data transaction via said PCI bus, said data transaction consequent from said grant to said high priority PCI agent from said arbiter.

Claim 5

The system of claim 1, wherein said low priority PCI agent has a higher priority than said interim low priority PCI agent such that said arbiter grants said PCI bus to said low priority PCI agent prior to said interim low priority PCI agent where said interim low priority PCI agent and said low priority PCI agent both are requesting ownership of said PCI bus.

Claim 6

The system of claim 1, wherein said interim low priority PCI agent reverts to said high priority PCI agent subsequent to said grant to said low priority PCI agent such that said high priority PCI agent again has a higher priority than said low priority PCI agent.

Claim 7

The system of claim 1, wherein a plurality of interim low priority PCI agents are prioritized with respect to each respective one of said plurality of interim low priority PCI agents.

Claim 8

A programmable priority arbitration system for interfacing a plurality of a peripheral component interconnect (PCI) agents coupled to a PCI bus such that high priority PCI agents are satisfied without starving low priority PCI agents, comprising: a PCI bus adapted to transmit data signals thereon; a high priority PCI agent coupled to said PCI bus; a low priority PCI agent coupled to said PCI bus; an arbiter coupled to said high priority PCI agent and said low priority PCI agent via said PCI bus; said arbiter granting ownership of said PCI bus to said high priority PCI agent, said high priority PCI agent becoming an interim low priority PCI agent after a first number of transactions by said high priority PCI agent, said first number of transactions corresponding to a first allocation factor, said first allocation factor being programmable, said low priority PCI agent having a higher priority than said interim low priority PCI agent; and said interim low priority PCI agent reverting to said high priority PCI agent subsequent to a second number of transactions by said low priority PCI agent, said second number of transactions corresponding to a second allocation factor, said second allocation factor being programmable, said arbiter granting ownership of said PCI bus to said low priority PCI agent before granting ownership of said PCI bus to said interim low priority PCI agent such that said low priority PCI agent is not prevented from accessing said PCI bus by said high priority PCI agent, and wherein said high priority PCI agent becomes said interim low priority PCI agent, said interim low priority PCI agent being the lowest priority of a plurality of PCI agents requesting ownership of said PCI bus.

Claim 9

A programmable priority arbitration system for interfacing a plurality of a peripheral component interconnect (PCI) agents coupled to a PCI bus such that high priority PCI agents are satisfied without starving low priority PCI agents, comprising: a PCI bus adapted to transmit data signals thereon; a high priority PCI agent coupled to said PCI bus; a low priority PCI agent coupled to said PCI bus; an arbiter coupled to said high priority PCI agent and said low priority PCI agent via said PCI bus; said arbiter granting ownership of said PCI bus to said high priority PCI agent, said high priority PCI agent becoming an interim low priority PCI agent after a first number of transactions by said high priority PCI agent, said first number of transactions corresponding to a first allocation factor, said first allocation factor being programmable, said low priority PCI agent having a higher priority than said interim low priority PCI agent; and said interim low priority PCI agent reverting to said high priority PCI agent subsequent to a second number of transactions by said low priority PCI agent, said second number of transactions corresponding to a second allocation factor, said second allocation factor being programmable, said arbiter granting ownership of said PCI bus to said low priority PCI agent before granting ownership of said PCI bus to said interim low priority PCI agent such that said low priority PCI agent is not prevented from accessing said PCI bus by said high priority PCI agent, and wherein said high priority PCI agent becomes said interim low priority PCI agent, said interim low priority PCI agent being the lowest priority of a plurality of PCI agents requesting ownership of said PCI bus.

Claim 10

The system of claim 7, wherein said arbiter grants ownership of said PCI bus to said high priority PCI agent, said high priority PCI agent being the highest priority of a plurality of PCI agents requesting ownership of said PCI bus.

Claim 11

The system of claim 7, wherein a plurality of interim low priority PCI agents are prioritized with respect to each respective one of said plurality of interim low priority PCI agents.

Claim 12

The system of claim 7, wherein said high priority PCI agent becomes said interim low priority PCI agent subsequent to starting said first number of data transactions corresponding to said first allocation factor, said number of data transactions consequent from at least one grant from said arbiter.

Claim 13

The system of claim 7, wherein said low priority PCI agent has a higher priority than said interim low priority PCI agent such that said arbiter grants said PCI bus to said low priority PCI agent prior to said interim low priority PCI agent, wherein said interim low priority PCI agent and said low priority PCI agent are both requesting ownership of said PCI bus.

Claim 14

The system of claim 7, wherein said interim low priority PCI agent reverts to said high priority PCI agent subsequent to said second number of transactions by said low priority PCI agent such that said high priority PCI agent again has a higher priority than said low priority PCI agent.

Claim 15

The system of claim 7, wherein a first amount of bandwidth of said PCI bus is granted to said high priority PCI agent and a second amount of bandwidth of said PCI bus is granted to said low priority PCI agent, said first amount and said second amount corresponding to said first allocation factor and said second allocation factor, wherein said first and second allocation factors are programmable to ensure respective minimum access to said PCI bus.

Claim 16

In a priority arbitration system for interfacing a plurality of a peripheral component interconnect (PCI) agents coupled to a PCI bus, a process of allocating access to the PCI bus such that high priority PCI agents are satisfied without starving low priority PCI agents, the process comprising the steps of: a) receiving a request for ownership of a PCI bus from a first PCI agent coupled to said PCI bus; b) receiving a request for ownership of said PCI bus from a second PCI agent coupled to said PCI bus; c) granting ownership of said PCI bus to said first PCI agent, wherein said first PCI agent is a higher priority than said second PCI agent; d) converting said first PCI agent to an interim low priority PCI agent such that said second PCI agent is a higher priority; e) granting ownership of said PCI bus to said second PCI agent such that said second PCI agent is not prevented from accessing said PCI bus by said first PCI agent; f) reverting said first PCI agent to a high priority PCI agent subsequent to granting ownership to said second PCI agent; and g) converting said high priority PCI agent to said interim low priority PCI agent, said interim low priority PCI agent having the lowest priority of a plurality of PCI agents requesting ownership of said PCI bus.

Claim 17

In a priority arbitration system for interfacing a plurality of a peripheral component interconnect (PCI) agents coupled to a PCI bus, a process of allocating access to the PCI bus such that high priority PCI agents are satisfied without starving low priority PCI agents, the process comprising the steps of: a) receiving a request for ownership of a PCI bus from a first PCI agent coupled to said PCI bus; b) receiving a request for ownership of said PCI bus from a second PCI agent coupled to said PCI bus; c) granting ownership of said PCI bus to said first PCI agent, wherein said first PCI agent is a higher priority than said second PCI agent; d) converting said first PCI agent to an interim low priority PCI agent such that said second PCI agent is a higher priority; e) granting ownership of said PCI bus to said second PCI agent such that said second PCI agent is not prevented from accessing said PCI bus by said first PCI agent; f) reverting said first PCI agent to a high priority PCI agent subsequent to granting ownership to said second PCI agent; and g) converting said high priority PCI agent to said interim low priority PCI agent, said interim low priority PCI agent having the lowest priority of a plurality of PCI agents requesting ownership of said PCI bus.

Claim 18

The process of claim 14, further including the step of granting ownership of said PCI bus to said high priority PCI agent, said high priority PCI agent being the highest priority PCI agent out of a plurality of PCI agents requesting ownership of said PCI bus.

Claim 19

The process of claim 14 further including the step of prioritizing a plurality of interim low priority PCI agents with respect to each respective one of said plurality of interim low priority PCI agents.

Claim 20

The system of claim 14, further including the step of converting said high priority PCI agent to said interim low priority PCI agent subsequent to starting a data transaction via said PCI bus, said data transaction consequent from a grant to said high priority PCI agent from an arbiter.

Claim 21

The system of claim 14, further including the step of granting said PCI bus to said low priority PCI agent prior to said interim low priority PCI agent wherein said interim low priority PCI agent and said low priority PCI agent both are requesting ownership of said PCI bus.