Method of passivating semiconductor wafers

Claim 1

A method of processing a semiconductor wafer to provide a composite passivation overcoat layer over a final patterned metal layer and to alleviate stress cracking tendency in the passivation layer, the method comprising the following steps: applying and patterning a final metal layer to define conductive final upper metal runners projecting atop the wafer, the final upper conductive metal runners projecting outwardly from the wafer at given distances, at least some immediately adjacent of the conductive metal runners being spaced from one another 1.2 microns or less, said at least some immediately adjacent runners having outermost flat planar surfaces elevationally positioned at a common given distance from the wafer; applying a first passivation layer of undoped SiO 2 which is deposited by a chemical vapor deposition method atop the wafer and final metal layer to a thickness which is greater than the given distance of a furthest projecting final metal runner, the first undoped SiO 2 passivation layer being in substantial contact with the outermost flat planar conductive metal runner surfaces; chemical-mechanical polishing the undoped SiO 2 passivation layer downwardly to provide a completely flat planar passivation layer of undoped SiO 2 having a completely flat upper surface at a point on the wafer which is elevationally above all of the underlying conductive metal runners; and applying a completely flat planar passivation overcoating layer of Si 3 N 4 by plasma enhanced chemical vapor deposition using SiH 4 and NH 3 atop the chemical-mechanical polished planarized passivation layer of undoped SiO 2 to impart mechanical protection, chemical diffusion protection, and a moisture barrier to the wafer, the completely flat planarity of the passivation undoped SiO 2 layer and the Si 3 N 4 passivation overcoating layer resulting in greater stress cracking alleviation than if such completely flat planar layers were not present; and selectively etching the Si 3 N 4 overcoating layer and undoped SiO 2 underlying passivation layer to bonding pads associated with the final metal runners.

Claim 2

A method of processing a semiconductor wafer to provide a composite passivation overcoat layer over a final patterned metal layer and to alleviate stress cracking tendency in the passivation layer, the method comprising the following steps: applying and patterning a final metal layer to define conductive final upper metal runners projecting atop the wafer, the final upper conductive metal runners projecting outwardly from the wafer at given distances, at least some immediately adjacent of the conductive metal runners being spaced from one another 1.2 microns or less, said at least some immediately adjacent runners having outermost flat planar surfaces elevationally positioned at a common given distance from the wafer; applying a first passivation layer of undoped SiO 2 which is deposited by a chemical vapor deposition method atop the wafer and final metal layer to a thickness which is greater than the given distance of a furthest projecting final metal runner, the first undoped SiO 2 passivation layer being in substantial contact with the outermost flat planar conductive metal runner surfaces; chemical-mechanical polishing the undoped SiO 2 passivation layer downwardly to provide a completely flat planar passivation layer of undoped SiO 2 having a completely flat upper surface at a point on the wafer which is elevationally above all of the underlying conductive metal runners; and applying a completely flat planar passivation overcoating layer of Si 3 N 4 by plasma enhanced chemical vapor deposition using SiH 4 and NH 3 atop the chemical-mechanical polished planarized passivation layer of undoped SiO 2 to impart mechanical protection, chemical diffusion protection, and a moisture barrier to the wafer, the completely flat planarity of the passivation undoped SiO 2 layer and the Si 3 N 4 passivation overcoating layer resulting in greater stress cracking alleviation than if such completely flat planar layers were not present; and selectively etching the Si 3 N 4 overcoating layer and undoped SiO 2 underlying passivation layer to bonding pads associated with the final metal runners.