Memory cells for field programmable memory array

Claim 2

A programmable memory array comprising a plurality of memory sub-arrays programable into a plurality of access modes, at least one of said sub-arrays including: a memory cell for holding data; a first word line that propagates a first select signal; a first bit line; a first selective coupler disposed between said first bit line and said memory cell, selectively coupling said first bit line and said memory cell in accordance with said first select signal for propagating a signal therebetween; an output interface connected to said memory cell for carrying a signal from said memory cell; and an additional data line connected to said memory cell for carrying a signal to said memory cell to enable at least some of said plurality of access modes.

Claim 3

A programmable memory array according to claim 1, wherein said first select signal is a write enable signal and said first bit line carries data to be stored in said memory cell when said first selective coupler is enabled by the write enable signal, said output interface comprising: a second bit line; a second word line that propagates a read enable signal; and a second selective coupler disposed between said second bit line and said memory cell, selectively coupling said second bit line and said memory cell for enabling reading of the data of said memory cell when enabled by the read enable signal.

Claim 4

A programmable memory circuit comprising: a memory cell for holding data; a first word line that propagates a first select signal; a first bit line; a first selective coupler disposed between said first bit line and said memory cell, selectively coupling said first bit line and said memory cell in accordance with said first select signal for propagating a signal therebetween; an output interface connected to said memory cell for carrying a signal from said memory cell; and an additional data line connected to said memory cell for carrying a signal to said memory cell, wherein said first select signal is a write enable signal and said first bit line carries data to be stored in said memory cell when said first selective coupler is enabled by the write enable signal, said output interface comprising: a second bit line; a second word line that propagates a read enable signal; and a second selective coupler disposed between said second bit line and said memory cell, selectively coupling said second bit line and said memory cell for enabling reading of the data of said memory cell when enabled by the read enable signal, the memory circuit further comprising: a third bit line for carrying alternative data to be stored in said memory cell; a third word line that propagates an alternative write enable signal; and a third selective coupler disposed between said third bit line and said additional data line, selectively coupling said third bit line and said additional data line for propagating the alternative data to said memory cell when enabled by the alternative write enable signal.

Claim 5

A programmable memory circuit comprising: a memory cell for holding data; a first word line that propagates a first select signal; a first bit line; a first selective coupler disposed between said first bit line and said memory cell, selectively coupling said first bit line and said memory cell in accordance with said first select signal for propagating a signal therebetween; an output interface connected to said memory cell for carrying a signal from said memory cell; and an additional data line connected to said memory cell for carrying a signal to said memory cell, wherein said first select signal is a write enable signal and said first bit line carries data to be stored in said memory cell when said first selective coupler is enabled by the write enable signal, said output interface comprising: a second bit line; a second word line that propagates a read enable signal; and a second selective coupler disposed between said second bit line and said memory cell, selectively coupling said second bit line and said memory cell for enabling reading of the data of said memory cell when enabled by the read enable signal, the memory circuit further comprising: a third bit line for carrying alternative data to be stored in said memory cell; a third word line that propagates an alternative write enable signal; and a third selective coupler disposed between said third bit line and said additional data line, selectively coupling said third bit line and said additional data line for propagating the alternative data to said memory cell when enabled by the alternative write enable signal.

Claim 6

A programmable memory array comprising a plurality of memory sub-arrays programable into a plurality of access modes, at least one of said sub-arrays including: a memory cell for holding data; a plurality of word lines, each word line of said plurality of word lines propagating an associated enable signal; a plurality of bit lines; and a plurality of selective couplers, each selective coupler of said plurality of selective couplers being disposed between said memory cell and an associated bit line of said plurality of bit lines, selectively coupling said associated bit line and said memory cell for propagating a signal therebetween when enabled by the enable signal of an associated word line of said plurality of word lines to enable at least some of said plurality of access modes.

Claim 7

A programmable memory array comprising a plurality of memory sub-arrays programable into a plurality of access modes, at least one of said sub-arrays including: a memory cell for holding data; a plurality of word lines, each word line of said plurality of word lines propagating an associated enable signal; a plurality of bit lines; and a plurality of selective couplers, each selective coupler of said plurality of selective couplers being disposed between said memory cell and an associated bit line of said plurality of bit lines, selectively coupling said associated bit line and said memory cell for propagating a signal therebetween when enabled by the enable signal of an associated word line of said plurality of word lines to enable at least some of said plurality of access modes.

Claim 8

A programmable memory circuit comprising: a memory cell for holding data; a plurality of word lines, each word line of said plurality of word lines propagating an associated enable signal; a plurality of bit lines; and a plurality of selective couplers, each selective coupler of said plurality of selective couplers being disposed between said memory cell and an associated bit line of said plurality of bit lines, selectively coupling said associated bit line and said memory cell for propagating a signal therebetween when enabled by the enable signal of an associated word line of said plurality of word lines, wherein: a reset word line of said plurality of word lines propagates a reset enable signal as its associated enable signal; a reset bit line of said plurality of bit lines is coupled to a fixed voltage source for propagating a reset level; and a first selective coupler of the plurality of selective couplers, disposed between said reset bit line and said memory cell, selectively couples said memory cell to said reset bit line for storing the reset level thereof in said memory cell when enabled by the reset enable signal of said reset word line.

Claim 9

A programmable memory circuit comprising: a memory cell for holding data; a plurality of word lines, each word line of said plurality of word lines propagating an associated enable signal; a plurality of bit lines; and a plurality of selective couplers, each selective coupler of said plurality of selective couplers being disposed between said memory cell and an associated bit line of said plurality of bit lines, selectively coupling said associated bit line and said memory cell for propagating a signal therebetween when enabled by the enable signal of an associated word line of said plurality of word lines, wherein: a reset word line of said plurality of word lines propagates a reset enable signal as its associated enable signal; a reset bit line of said plurality of bit lines is coupled to a fixed voltage source for propagating a reset level; and a first selective coupler of the plurality of selective couplers, disposed between said reset bit line and said memory cell, selectively couples said memory cell to said reset bit line for storing the reset level thereof in said memory cell when enabled by the reset enable signal of said reset word line.

Claim 10

A programmable memory circuit comprising: a memory cell for holding data; a plurality of word lines, each word line of said plurality of word lines propagating an associated enable signal; a plurality of bit lines; and a plurality of selective couplers, each selective coupler of said plurality of selective couplers being disposed between said memory cell and an associated bit line of said plurality of bit lines, selectively coupling said associated bit line and said memory cell for propagating a signal therebetween when enabled by the enable signal of an associated word line of said plurality of word lines, wherein said memory cell is part of a memory array associated with a Field Programmable Gate Array (FPGA), wherein: a state machine of said FPGA provides the FPGA access to said memory array; a program word line of said plurality of word lines propagates a program enable signal as effected by said state machine; a program bit line of said plurality of bit lines propagates program data from said state machine; and a first selective coupler of the plurality of selective couplers, disposed between said memory cell and said program bit line, selectively couples said cell to said program bit line for storing the program data from said state machine in said memory cell when enabled by the program enable signal of said program word line.

Claim 11

A programmable memory circuit comprising: a memory cell for holding data; a plurality of word lines, each word line of said plurality of word lines propagating an associated enable signal; a plurality of bit lines; and a plurality of selective couplers, each selective coupler of said plurality of selective couplers being disposed between said memory cell and an associated bit line of said plurality of bit lines, selectively coupling said associated bit line and said memory cell for propagating a signal therebetween when enabled by the enable signal of an associated word line of said plurality of word lines, wherein said memory cell is part of a memory array associated with a Field Programmable Gate Array (FPGA), wherein: a state machine of said FPGA provides the FPGA access to said memory array; a program word line of said plurality of word lines propagates a program enable signal as effected by said state machine; a program bit line of said plurality of bit lines propagates program data from said state machine; and a first selective coupler of the plurality of selective couplers, disposed between said memory cell and said program bit line, selectively couples said cell to said program bit line for storing the program data from said state machine in said memory cell when enabled by the program enable signal of said program word line.

Claim 12

A programmable memory circuit according to claim 6, wherein: a secondary word line of said plurality of word lines propagates a secondary enable signal; a secondary bit line of said plurality of bit lines propagates secondary data of a secondary source; and a second selective coupler of the plurality of selective couplers, disposed between said memory cell and said secondary bit line, selectively couples said memory cell to said secondary bit line for storing the secondary data in said memory cell when enabled by the secondary enable signal of said secondary word line.

Claim 13

A programmable memory circuit comprising: a memory cell for holding data; a plurality of word lines, each word line of said plurality of word lines propagating an associated enable signal; a plurality of bit lines; and a plurality of selective couplers, each selective coupler of said plurality of selective couplers being disposed between said memory cell and an associated bit line of said plurality of bit lines, selectively coupling said associated bit line and said memory cell for propagating a signal therebetween when enabled by the enable signal of an associated word line of said plurality of word lines, wherein said memory cell is part of a memory array, said programmable memory circuit further comprising: a serial input for receiving serial input data; a primary selective coupler disposed between said serial input and said memory cell, for selectively propagating serial input data of said serial input to said memory cell for storage when enabled by a primary scan clock; a secondary memory cell for holding data; and a secondary selective coupler disposed between said memory cell and said secondary memory cell, selectively propagating data of said memory cell to said secondary memory cell when enabled by a secondary scan clock; whereby said memory cell may receive data from one of said plurality of bit lines, or alternatively from said serial input, via the associated enable signal or the primary scan clock respectively.

Claim 14

A programmable memory circuit comprising: a memory cell for holding data; a plurality of word lines, each word line of said plurality of word lines propagating an associated enable signal; a plurality of bit lines; and a plurality of selective couplers, each selective coupler of said plurality of selective couplers being disposed between said memory cell and an associated bit line of said plurality of bit lines, selectively coupling said associated bit line and said memory cell for propagating a signal therebetween when enabled by the enable signal of an associated word line of said plurality of word lines, wherein said memory cell is part of a memory array, said programmable memory circuit further comprising: a serial input for receiving serial input data; a primary selective coupler disposed between said serial input and said memory cell, for selectively propagating serial input data of said serial input to said memory cell for storage when enabled by a primary scan clock; a secondary memory cell for holding data; and a secondary selective coupler disposed between said memory cell and said secondary memory cell, selectively propagating data of said memory cell to said secondary memory cell when enabled by a secondary scan clock; whereby said memory cell may receive data from one of said plurality of bit lines, or alternatively from said serial input, via the associated enable signal or the primary scan clock respectively.

Claim 15

A programmable memory circuit according to claim 8 further comprising: an N-bit address input for addressing said memory array; and an address decoder circuit, providing said associated enable signal upon decoding a specific address of said N-bit address input.

Claim 16

A programmable memory circuit comprising an array of bit/word line addressable memory cells including: a first memory cell addressable per a first word line for enabling primary data access thereto; a second memory cell addressable per a second word line, for enabling primary data access thereto; a transfer cell disposed intermediate said first memory cell and said second memory cell for providing intermediate data storage; a first selective coupler enabled per a first clock for selectively coupling said transfer cell and said first memory cell, enabling data propagation therebetween; and a second selective coupler enabled per a second clock for selectively coupling said transfer cell and said second memory cell, enabling data propagation therebetween; whereby said first and second clocks are operated sequentially for transferring data from one of said first and second memory cells to the other.

Claim 17

A programmable memory circuit comprising an array of bit/word line addressable memory cells including: a first memory cell addressable per a first word line for enabling primary data access thereto; a second memory cell addressable per a second word line, for enabling primary data access thereto; a transfer cell disposed intermediate said first memory cell and said second memory cell for providing intermediate data storage; a first selective coupler enabled per a first clock for selectively coupling said transfer cell and said first memory cell, enabling data propagation therebetween; and a second selective coupler enabled per a second clock for selectively coupling said transfer cell and said second memory cell, enabling data propagation therebetween; whereby said first and second clocks are operated sequentially for transferring data from one of said first and second memory cells to the other.

Claim 18

A programmable memory circuit according to claim 10, further comprising means for providing said first clock as a first phase push clock and said second clock as a second phase push clock in sequence for transferring data from said first memory cell to said second memory cell.

Claim 19

A programmable memory circuit according to claim 11, wherein: said transfer cell has an input for receiving data, the intermediate data stored therein being updated in accordance with the data received at said input, and an output for sending out data in accordance with the intermediate data stored therein; each of said first and second memory cells has an input for receiving data, data stored therein being updated in accordance with data received at said input, and an output for sending out data in accordance with the data stored therein; said first selective coupler is disposed between the output of said first memory cell and the input of said transfer cell; and said second selective coupler is disposed between the output of said transfer cell and the input of said second memory cell.

Claim 20

A programmable memory circuit according to claim 12, further comprising: a third selective coupler enabled per a first phase pop clock for selectively coupling the output of said secondary memory cell to the input of said transfer cell, enabling data transfer from said second memory cell to said transfer cell; a fourth selective coupler enabled per a second phase pop clock for selectively coupling the output of said transfer cell to the input of said first memory cell, enabling data transfer from said transfer cell to said first memory cell; and means for providing the first phase pop clock and the second phase pop clock sequentially for transferring data of said secondary memory cell to said first memory cell.