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US6087733A Expired / Lapsed US ⏱️ 0.0 years remaining

Sacrificial erosion control features for chemical-mechanical polishing process

Assignee: Intel Corp
•
Filing: 1998-06-12
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Granted: 2000-07-11
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Expires: 2018-06-12
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Abstract

Abstract A method and apparatus for compensating for the effects of nonuniform planarization in chemical-mechanical polishing (CMP) such as the erosion occurring from the removal of titanium nitride/tungsten films is disclosed. In the context of alignment marks, dummy marks are disposed on both sides of the actual alignment marks providing a similar feature density as the alignment marks. During the CMP, the dummy marks reside in the area of nonuniform erosion, leaving the actual marks in an area of uniform erosion. The present invention may also be used to control underlayer erosion variations in the high feature density device areas adjacent to the low feature density open areas by providing dummy features in the low feature density areas.

Inventors

  • 👤 Michael A. Maxim
  • 👤 Michael Kocsis
  • 👤 Ning Hsieh
  • 👤 Matthew Prince
  • 👤 Kenneth C. Cadien

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 08:46
CPC Classifications
H; H10; H10W; H10W46/00; H10P; H10P52/00; H10P52/40; H10P52/403; H10W20/00; H10W20/01; H10W20/031; H10W20/062; H10W46/101; H10W46/301; H10W46/501; H10W46/503

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 91 words
A semiconductor wafer including: a plurality of parallel alignment markers in a scribe line region of the wafer comprising metal filled trenches having a predetermined pitch formed in a dielectric layer; a first plurality of parallel dummy markers comprising metal filled trenches having approximately the predetermined pitch formed in the dielectric layer adjacent to one side of the alignment markers; and a second plurality of parallel dummy markers comprising metal filled trenches having approximately the predetermined pitch formed in the dielectric layer adjacent to the other sides of the alignment markers.
Claim 2
Dependent Claim 91 words
A semiconductor wafer including: a plurality of parallel alignment markers in a scribe line region of the wafer comprising metal filled trenches having a predetermined pitch formed in a dielectric layer; a first plurality of parallel dummy markers comprising metal filled trenches having approximately the predetermined pitch formed in the dielectric layer adjacent to one side of the alignment markers; and a second plurality of parallel dummy markers comprising metal filled trenches having approximately the predetermined pitch formed in the dielectric layer adjacent to the other sides of the alignment markers.
Claim 3
Dependent Claim 11 words
The semiconductor wafer of claim 1 wherein the metal is tungsten.
Claim 4
Dependent Claim 21 words
The semiconductor wafer defined by claim 1 wherein the first and second plurality each comprise approximately five or more dummy marks.

References Cited (Backward Citations)

US3825442A Cited
US4775550A Cited
US5278105A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-07-11 2004-01-10 2004-07-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-07-11 2008-01-10 2008-07-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-07-11 2012-01-10 2012-07-11 $7700.00 Window Closed / Lapsed

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