US6141287A
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US
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Memory architecture with multilevel hierarchy
Assignee: Infineon Technologies AG
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Filing: 1998-09-16
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Granted: 2000-10-31
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Expires: 2018-09-16
Abstract
Abstract The memory is made up of memory cells disposed in a memory architecture with multilevel hierarchy. Many external connection ports are provided. Such memories are generally called multiport memories. The novel multiport memory architecture with multilevel hierarchy typically has one-port memory cells in the lowermost hierarchical level. The memory blocks in the respectively higher hierarchical levels are each made up of memory blocks from the next lower hierarchical level. By the defined multiport memory architecture with multilevel hierarchy, the expenditure for surface area on the chip can advantageously be reduced. The memory blocks in the hierarchical levels can, depending on requirements, be disposed in a memory block matrix in a switching network, a banking technique arrangement, and so forth. Depending on the desired application, the greatest possible freedom of design is provided. The multiport memory architecture also has a circuit for handling access contentions. The novel memory architecture can be applied to all memory technologies as well as to logic technologies.
Inventors
- 👤 Hans-Jurgen Mattausch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 01:55
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G06; G06F; G06F12/00
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
118 words
A memory architecture, comprising: a plurality of hierarchical levels, including a lowermost hierarchical level and at least one higher hierarchical level; at least one memory block in each of said hierarchical levels, said memory block in said lowermost hierarchical level including individual memory cells, and each next-higher hierarchical level including memory blocks formed by memory blocks of a respectively next-lower hierarchical level; decoder devices in each of said hierarchical levels for driving, reading, and writing said memory blocks; at least one I/O interface with a plurality of I/O ports being driveable in parallel simultaneously and independently of one another; and an address selection circuit and a port selection buffer circuit in at least one of said hierarchical levels.
Claim 2
Dependent Claim
118 words
A memory architecture, comprising: a plurality of hierarchical levels, including a lowermost hierarchical level and at least one higher hierarchical level; at least one memory block in each of said hierarchical levels, said memory block in said lowermost hierarchical level including individual memory cells, and each next-higher hierarchical level including memory blocks formed by memory blocks of a respectively next-lower hierarchical level; decoder devices in each of said hierarchical levels for driving, reading, and writing said memory blocks; at least one I/O interface with a plurality of I/O ports being driveable in parallel simultaneously and independently of one another; and an address selection circuit and a port selection buffer circuit in at least one of said hierarchical levels.
Claim 3
Dependent Claim
20 words
The memory architecture according to claim 1, wherein said memory block in the lowermost hierarchical level comprises one-port memory cells.
Claim 4
Dependent Claim
67 words
The memory architecture according to claim 1, which further comprises an access contention resolution circuit in at least one of said hierarchical levels, said access contention resolution circuit, in event of an access contention among a plurality of I/O ports of a given memory block, enabling one of the I/O ports involved in the access contention and blocking all other I/O ports involved in the access contention.
Claim 5
Dependent Claim
31 words
The memory architecture according to claim 3, wherein said access contention resolution circuit is adapted to execute a prioritizing algorithm for prioritizing the I/O ports in accordance with a significance thereof.
Claim 6
Dependent Claim
43 words
The memory architecture according to claim 1, wherein said memory blocks in at least one of said hierarchical levels are disposed in matrix form in a memory block matrix with a first number of matrix rows and a second number of matrix columns.
Claim 7
Dependent Claim
23 words
The memory architecture according to claim 5, wherein one of the first number and the second number is an integer multiple of 2.
Claim 8
Dependent Claim
29 words
The memory architecture according to claim 5, wherein said memory block matrix includes a row decoder for selecting a row in said memory block matrix via corresponding address bits.
Claim 9
Dependent Claim
29 words
The memory architecture according to claim 5, wherein said memory block matrix includes a column decoder for selecting a column in said memory block matrix via corresponding address bits.
Claim 10
Dependent Claim
26 words
The memory architecture according to claim 1, wherein said memory blocks in at least one of said hierarchical levels are arranged in a switching network arrangement.
Claim 11
Dependent Claim
26 words
The memory architecture according to claim 1, wherein said memory blocks in at least one of said hierarchical levels are arranged according to a banking technique.
Claim 12
Dependent Claim
11 words
A logic component, comprising the memory architecture according to claim 1.
Claim 13
Dependent Claim
15 words
The logic component according to claim 11, wherein said memory cells are EEPROM memory cells.
Claim 14
Dependent Claim
12 words
A dynamic memory component, comprising the memory architecture according to claim 1.
Claim 15
Dependent Claim
16 words
The dynamic memory component according to claim 13, wherein said memory cells are dynamic DRAM cells.
Claim 16
Dependent Claim
12 words
A static memory component, comprising the memory architecture according to claim 1.
Claim 17
Dependent Claim
16 words
The static memory component according to claim 15, wherein said memory cells are static SRAM cells.
Claim 18
Dependent Claim
11 words
A read-only memory, comprising the memory architecture according to claim 1.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-31 | 2004-05-01 | 2004-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-31 | 2008-05-01 | 2008-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-31 | 2012-05-01 | 2012-10-31 | $7700.00 | Window Closed / Lapsed |