Patent US6154413A successfully refreshed from Google Patents.
US6154413A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for designing a memory tile for use in a tiled memory
Assignee: NXP USA Inc
•
Filing: 1999-04-05
•
Granted: 2000-11-28
•
Expires: 2019-04-05
Abstract
Abstract A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c', 32c").
Inventors
- 👤 Michael L. Longwell
- 👤 William Daune Atwell
- 👤 Jeffrey Van Myers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:17
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/145; G11C5/02; G11C5/025; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008
Claims Analysis
Total Claims: 246
Claim 1
Independent Claim
63 words
A method for designing a memory tile for use in a tiled memory, comprising the steps of: designing a memory cell; arranging a plurality of said memory cells in a cell array; determining the charge requirements of said cell array; designing a charge source to supply said charge requirements; and integrating said charge source and said cell array to form said memory tile.
Claim 2
Independent Claim
63 words
A method for designing a memory tile for use in a tiled memory, comprising the steps of: designing a memory cell; arranging a plurality of said memory cells in a cell array; determining the charge requirements of said cell array; designing a charge source to supply said charge requirements; and integrating said charge source and said cell array to form said memory tile.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein each charge source is designed to include a plurality of atomic charge pumps.
Claim 4
Dependent Claim
17 words
The method of claim 2 wherein the plurality of atomic charge pumps are designed to operate sequentially.
Claim 5
Dependent Claim
19 words
The method of claim 3 wherein the number of atomic charge pumps operating sequentially is designed to be selectable.
Claim 6
Dependent Claim
36 words
The method of claim 4 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.
Claim 7
Dependent Claim
27 words
The method of claim 5 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.
Claim 8
Dependent Claim
27 words
The method of claim 6 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 9
Dependent Claim
28 words
The method of claim 7 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 10
Dependent Claim
16 words
The method of claim 8 wherein the fault logic is designed to include error correction logic.
Claim 11
Dependent Claim
21 words
The method of claim 9 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 12
Dependent Claim
53 words
The method of claim 10 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 13
Dependent Claim
57 words
The method of claim 11 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 14
Dependent Claim
18 words
The method of claim 12 wherein the memory cells are arranged in an array of rows and columns.
Claim 15
Dependent Claim
58 words
The method of claim 13 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 16
Dependent Claim
58 words
The method of claim 14 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 17
Dependent Claim
58 words
The method of claim 13 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 18
Dependent Claim
27 words
The method of claim 5 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 19
Dependent Claim
28 words
The method of claim 17 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 20
Dependent Claim
16 words
The method of claim 18 wherein the fault logic is designed to include error correction logic.
Claim 21
Dependent Claim
21 words
The method of claim 19 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 22
Dependent Claim
53 words
The method of claim 20 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 23
Dependent Claim
57 words
The method of claim 21 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 24
Dependent Claim
18 words
The method of claim 22 wherein the memory cells are arranged in an array of rows and columns.
Claim 25
Dependent Claim
58 words
The method of claim 23 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 26
Dependent Claim
58 words
The method of claim 24 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 27
Dependent Claim
58 words
The method of claim 23 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 28
Dependent Claim
28 words
The method of claim 4 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 29
Dependent Claim
16 words
The method of claim 27 wherein the fault logic is designed to include error correction logic.
Claim 30
Dependent Claim
21 words
The method of claim 28 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 31
Dependent Claim
53 words
The method of claim 29 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 32
Dependent Claim
57 words
The method of claim 30 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 33
Dependent Claim
18 words
The method of claim 31 wherein the memory cells are arranged in an array of rows and columns.
Claim 34
Dependent Claim
58 words
The method of claim 32 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 35
Dependent Claim
58 words
The method of claim 33 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 36
Dependent Claim
58 words
The method of claim 32 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 37
Dependent Claim
53 words
The method of claim 4 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 38
Dependent Claim
57 words
The method of claim 36 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 39
Dependent Claim
18 words
The method of claim 37 wherein the memory cells are arranged in an array of rows and columns.
Claim 40
Dependent Claim
58 words
The method of claim 38 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 41
Dependent Claim
58 words
The method of claim 39 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 42
Dependent Claim
58 words
The method of claim 38 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 43
Dependent Claim
36 words
The method of claim 1 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.
Claim 44
Dependent Claim
27 words
The method of claim 42 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.
Claim 45
Dependent Claim
27 words
The method of claim 43 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 46
Dependent Claim
28 words
The method of claim 44 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 47
Dependent Claim
16 words
The method of claim 45 wherein the fault logic is designed to include error correction logic.
Claim 48
Dependent Claim
21 words
The method of claim 46 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 49
Dependent Claim
53 words
The method of claim 47 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 50
Dependent Claim
57 words
The method of claim 48 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 51
Dependent Claim
18 words
The method of claim 49 wherein the memory cells are arranged in an array of rows and columns.
Claim 52
Dependent Claim
58 words
The method of claim 50 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 53
Dependent Claim
58 words
The method of claim 51 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 54
Dependent Claim
58 words
The method of claim 50 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 55
Dependent Claim
27 words
The method of claim 42 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 56
Dependent Claim
28 words
The method of claim 54 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 57
Dependent Claim
16 words
The method of claim 55 wherein the fault logic is designed to include error correction logic.
Claim 58
Dependent Claim
21 words
The method of claim 56 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 59
Dependent Claim
53 words
The method of claim 57 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 60
Dependent Claim
57 words
The method of claim 58 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 61
Dependent Claim
18 words
The method of claim 59 wherein the memory cells are arranged in an array of rows and columns.
Claim 62
Dependent Claim
58 words
The method of claim 60 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 63
Dependent Claim
58 words
The method of claim 61 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 64
Dependent Claim
58 words
The method of claim 60 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 65
Dependent Claim
28 words
The method of claim 1 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 66
Dependent Claim
16 words
The method of claim 64 wherein the fault logic is designed to include error correction logic.
Claim 67
Dependent Claim
21 words
The method of claim 65 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 68
Dependent Claim
53 words
The method of claim 66 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 69
Dependent Claim
57 words
The method of claim 67 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 70
Dependent Claim
18 words
The method of claim 68 wherein the memory cells are arranged in an array of rows and columns.
Claim 71
Dependent Claim
58 words
The method of claim 69 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 72
Dependent Claim
58 words
The method of claim 70 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 73
Dependent Claim
58 words
The method of claim 69 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 74
Dependent Claim
53 words
The method of claim 1 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 75
Dependent Claim
57 words
The method of claim 73 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in lace of a selected one of said memory cells.
Claim 76
Dependent Claim
18 words
The method of claim 74 wherein the memory cells are arranged in an array of rows and columns.
Claim 77
Dependent Claim
58 words
The method of claim 75 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 78
Dependent Claim
58 words
The method of claim 76 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 79
Dependent Claim
58 words
The method of claim 75 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 80
Dependent Claim
19 words
The method of claim 1 wherein the voltage reference is designed to include a plurality of atomic voltage references.
Claim 81
Dependent Claim
15 words
The method of claim 79 wherein the atomic voltage references are designed to operate simultaneously.
Claim 82
Dependent Claim
19 words
The method of claim 80 wherein the number of atomic voltage references operating simultaneously is designed to be selectable.
Claim 83
Dependent Claim
36 words
The method of claim 81 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.
Claim 84
Dependent Claim
27 words
The method of claim 82 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.
Claim 85
Dependent Claim
27 words
The method of claim 83 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 86
Dependent Claim
28 words
The method of claim 84 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 87
Dependent Claim
16 words
The method of claim 85 wherein the fault logic is designed to include error correction logic.
Claim 88
Dependent Claim
21 words
The method of claim 86 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 89
Dependent Claim
53 words
The method of claim 87 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 90
Dependent Claim
57 words
The method of claim 88 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 91
Dependent Claim
18 words
The method of claim 89 wherein the memory cells are arranged in an array of rows and columns.
Claim 92
Dependent Claim
58 words
The method of claim 90 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 93
Dependent Claim
58 words
The method of claim 91 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 94
Dependent Claim
58 words
The method of claim 90 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 95
Dependent Claim
27 words
The method of claim 82 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 96
Dependent Claim
28 words
The method of claim 94 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 97
Dependent Claim
16 words
The method of claim 95 wherein the fault logic is designed to include error correction logic.
Claim 98
Dependent Claim
21 words
The method of claim 96 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 99
Dependent Claim
53 words
The method of claim 97 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 100
Dependent Claim
57 words
The method of claim 98 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 101
Dependent Claim
18 words
The method of claim 99 wherein the memory cells are arranged in an array of rows and columns.
Claim 102
Dependent Claim
58 words
The method of claim 100 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 103
Dependent Claim
58 words
The method of claim 101 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 104
Dependent Claim
58 words
The method of claim 100 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 105
Dependent Claim
28 words
The method of claim 81 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 106
Dependent Claim
16 words
The method of claim 104 wherein the fault logic is designed to include error correction logic.
Claim 107
Dependent Claim
21 words
The method of claim 105 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 108
Dependent Claim
53 words
The method of claim 106 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 109
Dependent Claim
57 words
The method of claim 107 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 110
Dependent Claim
18 words
The method of claim 108 wherein the memory cells are arranged in an array of rows and columns.
Claim 111
Dependent Claim
58 words
The method of claim 109 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 112
Dependent Claim
58 words
The method of claim 110 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 113
Dependent Claim
58 words
The method of claim 109 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 114
Dependent Claim
53 words
The method of claim 81 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 115
Dependent Claim
57 words
The method of claim 113 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 116
Dependent Claim
18 words
The method of claim 114 wherein the memory cells are arranged in an array of rows and columns.
Claim 117
Dependent Claim
58 words
The method of claim 115 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 118
Dependent Claim
58 words
The method of claim 116 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 119
Dependent Claim
58 words
The method of claim 115 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 120
Dependent Claim
15 words
The memory tile of claim 1 wherein said memory tile further comprises access control logic.
Claim 121
Dependent Claim
17 words
The memory tile of claim 119 wherein the access control logic comprises address buffers and timing logic.
Claim 122
Dependent Claim
25 words
The memory tile of claim 1 wherein said memory tile further comprises data buffers coupled to the interface and to each of the memory cells.
Claim 123
Dependent Claim
29 words
The memory tile of claim 121 wherein said memory tile further comprises sense amplifiers coupled between each of the memory cells and a respective one of said data buffers.
Claim 124
Independent Claim
73 words
A method for designing an integrated circuit having a memory tile in a tiled memory, comprising the steps of: designing a memory cell; arranging a plurality of said memory cells in a cell array; determining the charge requirements of said cell array; designing a charge source to supply said charge requirements; and integrating said charge source and said cell array to form said memory tile in said tiled memory of said integrated circuit.
Claim 125
Independent Claim
73 words
A method for designing an integrated circuit having a memory tile in a tiled memory, comprising the steps of: designing a memory cell; arranging a plurality of said memory cells in a cell array; determining the charge requirements of said cell array; designing a charge source to supply said charge requirements; and integrating said charge source and said cell array to form said memory tile in said tiled memory of said integrated circuit.
Claim 126
Dependent Claim
19 words
The method of claim 123 wherein each charge source is designed to include a plurality of atomic charge pumps.
Claim 127
Dependent Claim
17 words
The method of claim 124 wherein the plurality of atomic charge pumps are designed to operate sequentially.
Claim 128
Dependent Claim
19 words
The method of claim 125 wherein the number of atomic charge pumps operating sequentially is designed to be selectable.
Claim 129
Dependent Claim
36 words
The method of claim 126 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.
Claim 130
Dependent Claim
27 words
The method of claim 127 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.
Claim 131
Dependent Claim
27 words
The method of claim 128 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 132
Dependent Claim
28 words
The method of claim 129 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 133
Dependent Claim
16 words
The method of claim 130 wherein the fault logic is designed to include error correction logic.
Claim 134
Dependent Claim
21 words
The method of claim 131 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 135
Dependent Claim
53 words
The method of claim 132 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 136
Dependent Claim
57 words
The method of claim 133 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 137
Dependent Claim
18 words
The method of claim 134 wherein the memory cells are arranged in an array of rows and columns.
Claim 138
Dependent Claim
58 words
The method of claim 135 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 139
Dependent Claim
58 words
The method of claim 136 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 140
Dependent Claim
58 words
The method of claim 135 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 141
Dependent Claim
27 words
The method of claim 127 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 142
Dependent Claim
28 words
The method of claim 139 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 143
Dependent Claim
16 words
The method of claim 140 wherein the fault logic is designed to include error correction logic.
Claim 144
Dependent Claim
21 words
The method of claim 141 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 145
Dependent Claim
53 words
The method of claim 142 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 146
Dependent Claim
57 words
The method of claim 143 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 147
Dependent Claim
18 words
The method of claim 144 wherein the memory cells are arranged in an array of rows and columns.
Claim 148
Dependent Claim
58 words
The method of claim 145 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 149
Dependent Claim
58 words
The method of claim 146 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 150
Dependent Claim
58 words
The method of claim 145 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 151
Dependent Claim
28 words
The method of claim 126 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 152
Dependent Claim
16 words
The method of claim 149 wherein the fault logic is designed to include error correction logic.
Claim 153
Dependent Claim
21 words
The method of claim 150 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 154
Dependent Claim
53 words
The method of claim 151 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 155
Dependent Claim
57 words
The method of claim 152 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 156
Dependent Claim
18 words
The method of claim 153 wherein the memory cells are arranged in an array of rows and columns.
Claim 157
Dependent Claim
58 words
The method of claim 154 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 158
Dependent Claim
58 words
The method of claim 155 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 159
Dependent Claim
58 words
The method of claim 154 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 160
Dependent Claim
53 words
The method of claim 126 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 161
Dependent Claim
57 words
The method of claim 158 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 162
Dependent Claim
18 words
The method of claim 159 wherein the memory cells are arranged in an array of rows and columns.
Claim 163
Dependent Claim
58 words
The method of claim 160 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 164
Dependent Claim
58 words
The method of claim 161 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 165
Dependent Claim
58 words
The method of claim 160 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 166
Dependent Claim
36 words
The method of claim 123 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.
Claim 167
Dependent Claim
27 words
The method of claim 164 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.
Claim 168
Dependent Claim
27 words
The method of claim 165 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 169
Dependent Claim
28 words
The method of claim 166 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 170
Dependent Claim
16 words
The method of claim 167 wherein the fault logic is designed to include error correction logic.
Claim 171
Dependent Claim
21 words
The method of claim 168 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 172
Dependent Claim
53 words
The method of claim 169 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 173
Dependent Claim
57 words
The method of claim 170 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 174
Dependent Claim
18 words
The method of claim 171 wherein the memory cells are arranged in an array of rows and columns.
Claim 175
Dependent Claim
58 words
The method of claim 172 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 176
Dependent Claim
58 words
The method of claim 173 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 177
Dependent Claim
58 words
The method of claim 172 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 178
Dependent Claim
27 words
The method of claim 164 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 179
Dependent Claim
28 words
The method of claim 176 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 180
Dependent Claim
16 words
The method of claim 177 wherein the fault logic is designed to include error correction logic.
Claim 181
Dependent Claim
21 words
The method of claim 178 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 182
Dependent Claim
53 words
The method of claim 179 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 183
Dependent Claim
57 words
The method of claim 180 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 184
Dependent Claim
18 words
The method of claim 181 wherein the memory cells are arranged in an array of rows and columns.
Claim 185
Dependent Claim
58 words
The method of claim 182 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 186
Dependent Claim
58 words
The method of claim 183 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 187
Dependent Claim
58 words
The method of claim 182 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 188
Dependent Claim
28 words
The method of claim 123 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 189
Dependent Claim
16 words
The method of claim 186 wherein the fault logic is designed to include error correction logic.
Claim 190
Dependent Claim
21 words
The method of claim 187 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 191
Dependent Claim
53 words
The method of claim 188 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 192
Dependent Claim
57 words
The method of claim 189 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 193
Dependent Claim
18 words
The method of claim 190 wherein the memory cells are arranged in an array of rows and columns.
Claim 194
Dependent Claim
58 words
The method of claim 191 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 195
Dependent Claim
58 words
The method of claim 192 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 196
Dependent Claim
58 words
The method of claim 191 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 197
Dependent Claim
53 words
The method of claim 123 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 198
Dependent Claim
57 words
The method of claim 195 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 199
Dependent Claim
18 words
The method of claim 196 wherein the memory cells are arranged in an array of rows and columns.
Claim 200
Dependent Claim
58 words
The method of claim 197 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 201
Dependent Claim
58 words
The method of claim 198 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 202
Dependent Claim
58 words
The method of claim 197 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 203
Dependent Claim
19 words
The method of claim 123 wherein the voltage reference is designed to include a plurality of atomic voltage references.
Claim 204
Dependent Claim
15 words
The method of claim 201 wherein the atomic voltage references are designed to operate simultaneously.
Claim 205
Dependent Claim
19 words
The method of claim 202 wherein the number of atomic voltage references operating simultaneously is designed to be selectable.
Claim 206
Dependent Claim
36 words
The method of claim 203 wherein each memory tile is designed to include a voltage level detector coupled to the charge source, the voltage level detector being designed to detect incorrect operation of said charge source.
Claim 207
Dependent Claim
27 words
The method of claim 204 wherein the voltage level detector is designed to provide an output signal in response to detecting incorrect operation of said charge source.
Claim 208
Dependent Claim
27 words
The method of claim 205 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 209
Dependent Claim
28 words
The method of claim 206 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 210
Dependent Claim
16 words
The method of claim 207 wherein the fault logic is designed to include error correction logic.
Claim 211
Dependent Claim
21 words
The method of claim 208 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 212
Dependent Claim
53 words
The method of claim 209 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 213
Dependent Claim
57 words
The method of claim 210 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 214
Dependent Claim
18 words
The method of claim 211 wherein the memory cells are arranged in an array of rows and columns.
Claim 215
Dependent Claim
58 words
The method of claim 212 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 216
Dependent Claim
58 words
The method of claim 213 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 217
Dependent Claim
58 words
The method of claim 212 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 218
Dependent Claim
27 words
The method of claim 204 wherein the voltage level detector is designed to disable said charge source in response to detecting incorrect operation of said charge source.
Claim 219
Dependent Claim
28 words
The method of claim 216 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 220
Dependent Claim
16 words
The method of claim 217 wherein the fault logic is designed to include error correction logic.
Claim 221
Dependent Claim
21 words
The method of claim 218 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 222
Dependent Claim
53 words
The method of claim 219 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 223
Dependent Claim
57 words
The method of claim 220 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 224
Dependent Claim
18 words
The method of claim 221 wherein the memory cells are arranged in an array of rows and columns.
Claim 225
Dependent Claim
58 words
The method of claim 222 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 226
Dependent Claim
58 words
The method of claim 223 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 227
Dependent Claim
58 words
The method of claim 222 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 228
Dependent Claim
28 words
The method of claim 203 wherein each memory tile is designed to include fault logic, coupled between the memory cells and the interface, to detect a bit error.
Claim 229
Dependent Claim
16 words
The method of claim 226 wherein the fault logic is designed to include error correction logic.
Claim 230
Dependent Claim
21 words
The method of claim 227 wherein the fault logic is designed to detect double bit errors and correct single bit errors.
Claim 231
Dependent Claim
54 words
The method of claim 228 wherein each memory tile is designed to include a n address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 232
Dependent Claim
57 words
The method of claim 229 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 233
Dependent Claim
18 words
The method of claim 230 wherein the memory cells are arranged in an array of rows and columns.
Claim 234
Dependent Claim
58 words
The method of claim 231 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 235
Dependent Claim
58 words
The method of claim 232 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 236
Dependent Claim
58 words
The method of claim 231 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 237
Dependent Claim
53 words
The method of claim 203 wherein each memory tile is designed to include an address decoder coupled to the interface and to each of the memory cells, to receive an address from said external logic via said interface and selectively couple one of said memory cells to said external logic via said interface.
Claim 238
Dependent Claim
57 words
The method of claim 235 wherein each memory tile is designed to include at least one redundant memory cell, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a redundancy control signal, said redundant memory cell to be addressed in place of a selected one of said memory cells.
Claim 239
Dependent Claim
18 words
The method of claim 236 wherein the memory cells are arranged in an array of rows and columns.
Claim 240
Dependent Claim
58 words
The method of claim 237 wherein each memory tile is designed to include at least one redundant row of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a row redundancy control signal, said redundant row to be addressed in place of a selected one of said rows.
Claim 241
Dependent Claim
58 words
The method of claim 238 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 242
Dependent Claim
58 words
The method of claim 237 wherein each memory tile is designed to include at least one redundant column of memory cells, and wherein the address decoder is designed to include redundancy control logic to enable, in response to a column redundancy control signal, said redundant column to be addressed in place of a selected one of said columns.
Claim 243
Dependent Claim
15 words
The memory tile of claim 123 wherein said memory tile further comprises access control logic.
Claim 244
Dependent Claim
17 words
The memory tile of claim 241 wherein the access control logic comprises address buffers and timing logic.
Claim 245
Dependent Claim
25 words
The memory tile of claim 123 wherein said memory tile further comprises data buffers coupled to the interface and to each of the memory cells.
Claim 246
Dependent Claim
29 words
The memory tile of claim 243 wherein said memory tile further comprises sense amplifiers coupled between each of the memory cells and a respective one of said data buffers.
References Cited (Backward Citations)
US5659519A
Cited
US5574697A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |