Layout designing method and layout designing apparatus

Claim 2

A hierarchical layout design method for a semiconductor device, comprising: determining layout positions in which hard macro blocks and a soft macro block are to be placed; forming a wiring which connects the hard macro blocks to each other using a path which passes above the soft macro block; forming cell rows in which cells are to be placed in the soft macro block; and forming an internal wiring of the soft macro block, wherein forming cell rows comprises: evaluation of an extent of an influence which a wiring passing above the soft macro block will exert on the internal wiring of the soft macro block; and a determination of an extending direction in which the cell rows are to extend in the soft macro block based on a result of said evaluation.

Claim 3

The hierarchical layout designing method according to claim 1, further comprising: correction of at least one of a shape and size of the soft macro block and at least one of a shape and size of the cell rows, in accordance with the extent of the influence which has been evaluated by said evaluation.

Claim 4

The hierarchical layout designing method according to claim 1, wherein said evaluation includes evaluating the extent of the influence which the wiring passing above the soft macro block will exert on the internal wiring of the soft macro block, based on wiring layers for forming the wiring passing above the soft macro blocks wiring directions and the number of wires forming the wiring.

Claim 5

The hierarchical layout designing method according to claim 1, wherein: said evaluation includes calculating a first cost and a second cost, said first cost being a cost when the cell rows are formed extending in a first direction, and said second cost being a cost when the cell rows are formed extending in a second direction; and by said determination, said first and second costs are compared with each other, and a direction in which a lower one of said first and second costs is attained is determined as extending direction of the cell rows.

Claim 6

The hierarchical layout designing method according to claim 1, wherein: by said evaluation, costs when a wiring formed from each of wiring layers passes above the soft macro block are calculated, and maximum values of the costs calculated in association with the wiring layers are obtained; and based on the obtained maximum values, the extending direction of the cell rows is determined through said determination.

Claim 7

The hierarchical layout designing method according to claim 1, wherein: said evaluation includes: calculating a first sum of a cost when a wiring extending in a first direction passes above the soft macro block and a cost when a wiring extending in a second direction passes above the soft macro, in the case where the cell rows are extending in the direction, and calculating a second sum of a cost when the wiring extending in the first direction passes above the soft macro block and a cost when the wiring extending in the second direction passes above the soft macro block, in the case where the cell rows are formed extending in the second direction; and through said determination, said first and second sums compared with each other, and a direction in which a lower of said first and second sums is attained is determined as the extending direction of the cell rows.

Claim 8

The hierarchical layout designing method according to claim 1, wherein: when a number of wiring layers is "n", said evaluation includes: calculating, in association with each of wiring layers, costs when a wiring extending in a first direction passes above the soft macro block and costs when a wiring extending in a second direction passes above the soft macro block, in the case where the cell rows are formed extending in the first direction, and calculating a first sum of a maximum value of the calculated costs when the wiring extending in the first direction passes above the soft macro block and a maximum value of the calculated costs when the wiring extending in the second direction passes above the soft macro block, and calculating, in association with each of the wiring layers, costs when the wiring extending in the first direction passes above the soft macro block and costs when the wiring extending in the second direction passes above the soft macro block, in the case where the cell rows are formed extending in the second direction, and calculating a second sum of a maximum value of the calculated costs when the wiring extending in the first direction passes above the soft macro block and a maximum value of the calculated costs when the wiring extending in the second direction passes above the soft macro block; and through said determination, said first sum and said second sum are compared with each other, and the cell rows are formed extending in the first direction when said first sum is smaller than said second sum, and the cell rows are formed extending in the second direction when said second sum is smaller than said first sum.

Claim 9

The hierarchical layout designing method according to claim 7, further comprising correcting at least one of a shape and size of the soft macro block and at least one of a shape and size of the cell rows, based on the costs calculated by said evaluation step.

Claim 10

A hierarchical layout designing apparatus comprising: means for arranging hard macro blocks and a soft macro block; means for forming a wiring which connects the hard macro blocks to each other using a path which passes above the soft macro block; evaluation means for evaluating an extent of an influence which a wiring passing above the soft macro block will exert on an internal wiring of the soft macro block; and formation means for forming the cell rows in the soft macro block after determining an extending direction in which the cell rows are to extend in the soft macro block, based on an extent of influence determined by the evaluation means.

Claim 11

A hierarchical layout designing apparatus comprising: means for arranging hard macro blocks and a soft macro block; means for forming a wiring which connects the hard macro blocks to each other using a path which passes above the soft macro block; evaluation means for evaluating an extent of an influence which a wiring passing above the soft macro block will exert on an internal wiring of the soft macro block; and formation means for forming the cell rows in the soft macro block after determining an extending direction in which the cell rows are to extend in the soft macro block, based on an extent of influence determined by the evaluation means.

Claim 12

The hierarchical layout designing apparatus according to claim 9, further comprising correction means for correcting at least one of a shape and size of the soft macro block and at least one of a shape and size of the cell rows, in accordance with the extent of the influence which has been evaluated by said evaluation means.

Claim 13

The hierarchical layout designing apparatus according to claim 9, wherein said evaluation means includes means for evaluating the extent of the influence which the wiring passing above the soft macro block will exert on the internal wiring of the soft macro block, based on wiring layers for forming the wiring passing above the soft macro block, wiring directions and the number of wires forming the wiring.

Claim 14

The hierarchical layout designing apparatus according to claim 9, wherein said evaluation means includes means for calculating a first cost and a second cost, said first cost being a cost when the cell rows are formed extending in a first direction, and said second cost being a cost when the cell rows are formed extending in a second direction; and said formation means includes means for comparing said first and second costs with each other and forming the cell rows after determining, as the extending direction of the cell rows, a direction in which a lower one of said first and second costs is attained.

Claim 15

The hierarchical layout designing apparatus according to claim 9, wherein said evaluation means includes means for calculating costs when a wiring formed from each of wiring layers passes above the soft macro block, and for calculating maximum values of the costs calculated in association with the wiring layers; and said formation means includes means for determining the extending direction of the cell rows, based on the obtained maximum values.

Claim 16

The hierarchical layout designing apparatus according to claim 9, wherein: said evaluation means includes means for calculating a first sum of a cost when a wiring extending in a first direction passes above the soft macro block and a cost when a wiring extending in a second direction passes above the soft macro, in the case where the cell rows are formed extending in the first direction, and means for calculating a second sum of a cost when the wiring extending in the first direction passes above the soft macro and a cost when the wiring extending in the second direction passes above the soft macro, in the case where the cell rows are formed extending in the second direction; and said formation means includes means for comparing said first and second sums with each other and determining, as the extending direction of the cell rows, a direction in which a lower one of said first and second sums is attained.

Claim 17

The hierarchical layout designing apparatus according to claim 9, wherein: when a number of wiring layers is "n", said evaluation means includes means for calculating, in association with each of wiring layers, costs when a wiring extending in a first direction passes above the soft macro block and costs when a wiring extending in a second direction passes above the soft macro block, in the case where the cell rows are formed extending in the first direction, and means for calculating a first sum of a maximum value of the calculated costs when the wiring extending in the first direction passes above the soft macro block and a maximum value of the calculated costs when the wiring extending in the second direction passes above the soft macro block, and means for calculating, in association with each of the wiring layers, costs when the wiring extending in the first direction passes above the soft macro block and costs when the wiring extending in the second direction passes above the soft macro block, in the case where the cell rows are formed extending in the second direction, and means for calculating a second sum of a maximum value of the calculated costs when the wiring extending in the first direction passes above the soft macro block and a maximum value of the calculated costs when the wiring extending in the second direction passes above the soft macro block; and said formation means includes means for comparing said first sum and said second sum with each other, and forming the cell rows so as to extend in the first direction when said first sum is smaller than said second sum and forming the cell rows so as to extend in the second direction when said second sum is smaller than said first sum.

Claim 18

The hierarchical layout designing apparatus according to claim 15, further comprising means for correcting at least one of a shape and size of the soft macro block and at least one of a shape and size of the cell rows, based on the costs calculated by said evaluation means.

Claim 19

A computer readable recording medium in which a program has been recorded, said program controlling a computer to execute a process for hierarchical layout design of a semiconductor device, the process comprising: determining layout positions in which hard macro blocks and a soft macro block are to be placed; forming a wiring which connects the hard macro blocks to each other using a path which passes above the soft macro block; evaluation of an influence which the wiring passing above the soft macro block will exert on an internal wiring of the soft macro block; and determining a direction in which the cell rows are to extend in the soft macro block based on a result of the evaluation.

Claim 20

A computer readable recording medium in which a program has been recorded, said program controlling a computer to execute a process for hierarchical layout design of a semiconductor device, the process comprising: determining layout positions in which hard macro blocks and a soft macro block are to be placed; forming a wiring which connects the hard macro blocks to each other using a path which passes above the soft macro block; evaluation of an influence which the wiring passing above the soft macro block will exert on an internal wiring of the soft macro block; and determining a direction in which the cell rows are to extend in the soft macro block based on a result of the evaluation.

Claim 21

The recording medium according to claim 17, wherein the process further comprises correcting at least one of a shape and size of the soft macro block and at least one of a shape and size of the cell rows, based on a result of said evaluation.