Method of fabricating a Bi-CMOS IC device including a self-alignment bipolar transistor capable of high speed operation

Claim 1

A method for producing a bipolar transistor and an MOS transistor, comprising the steps of: forming a gate insulation film in an MOS transistor region where the MOS transistor is to be formed and in a bipolar transistor region where the bipolar transistor is to be formed; forming a first conductive film and a first insulation film on the gate insulation film; removing the first insulation film, the first conductive film and the gate insulation film from the bipolar transistor region; removing the first insulation film from the MOS transistor region; forming a second conductive film on the first conductive film in a region where the first insulation film is removed; and performing an impurity ion implantation process whereby impurities are prevented from reaching the MOS transistor region through the second conductive film.

Claim 2

A method for producing a bipolar transistor and an MOS transistor, comprising the steps of: forming a gate insulation film in an MOS transistor region where the MOS transistor is to be formed and in a bipolar transistor region where the bipolar transistor is to be formed; forming a first conductive film and a first insulation film on the gate insulation film; removing the first insulation film, the first conductive film and the gate insulation film from the bipolar transistor region; removing the first insulation film from the MOS transistor region; forming a second conductive film on the first conductive film in a region where the first insulation film is removed; and performing an impurity ion implantation process whereby impurities are prevented from reaching the MOS transistor region through the second conductive film.

Claim 5

A method for producing a Bi-CMOS IC device, comprising the steps of: successively forming a gate insulation film, a first conductive film and a first insulation film on a semiconductor substrate including an MOS transistor region where an MOS transistor is to be formed and a bipolar transistor region where a bipolar transistor is to be formed; removing the first insulation film, the first conductive film and the gate insulation film from the bipolar transistor region; successively growing a second conductive film and a second insulation film over the semiconductor substrate; selectively etching the second insulation film and the second conductive film so as to form a base lead electrode and an insulation film on the base lead electrode; growing a third insulation film on an entire surface of the semiconductor substrate including an emitter region where an emitter is to be formed, the emitter region being surrounded by a side surface of the base lead electrode and the base lead electrode; anisotropically etching the third insulation film so as to leave a side wall on each side surface of the base lead electrode in the emitter region; removing the first insulation film; growing a third conductive film on the entire surface of the semiconductor substrate including an emitter electrode extraction opening defined by the side walls in the emitter region; and selectively etching the third conductive film and the first conductive film outside the bipolar transistor region so as to form an emitter electrode over the emitter electrode extraction opening and a gate electrode of the MOS transistor, the gate electrode including the third conductive film as an upper layer and the first conductive film as a lower layer.

Claim 6

A method for producing a Bi-CMOS IC device, comprising the steps of: successively forming a gate insulation film, a first conductive film and a first insulation film on a semiconductor substrate including an MOS transistor region where an MOS transistor is to be formed and a bipolar transistor region where a bipolar transistor is to be formed; removing the first insulation film, the first conductive film and the gate insulation film from the bipolar transistor region; successively growing a second conductive film and a second insulation film over the semiconductor substrate; selectively etching the second insulation film and the second conductive film so as to form a base lead electrode and an insulation film on the base lead electrode; growing a third insulation film on an entire surface of the semiconductor substrate including an emitter region where an emitter is to be formed, the emitter region being surrounded by a side surface of the base lead electrode and the base lead electrode; anisotropically etching the third insulation film so as to leave a side wall on each side surface of the base lead electrode in the emitter region; removing the first insulation film; growing a third conductive film on the entire surface of the semiconductor substrate including an emitter electrode extraction opening defined by the side walls in the emitter region; and selectively etching the third conductive film and the first conductive film outside the bipolar transistor region so as to form an emitter electrode over the emitter electrode extraction opening and a gate electrode of the MOS transistor, the gate electrode including the third conductive film as an upper layer and the first conductive film as a lower layer.