US6163495A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Architecture, method(s) and circuitry for low power memories
Assignee: Computer Circuit Operations LLC
•
Filing: 1999-09-17
•
Granted: 2000-12-19
•
Expires: 2019-09-17
Abstract
Abstract A circuit comprising a first and second bitline, a plurality of groups of memory cells and a control circuit. The first and second bitlines may each be configured to read and write to one or more of the plurality of groups of memory cells. Each of the plurality of bitline pairs may be interdigitated. The control circuit may be configured to select an active group of said plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.
Inventors
- 👤 Keith A. Ford
- 👤 Iulian C. Gradinariu
- 👤 Bogdan I. Georgescu
- 👤 Sean B. Mulholland
- 👤 John J. Silver
- 👤 Danny L. Rose
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:21
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; G11C8/00; G11C8/14; G11C8/12; G11C8/18
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
75 words
A circuit comprising: a first and a second bitline each configured to read arid write data to one or more of a plurality of groups of memory cells, wherein each of said plurality of groups of memory cells is interdigitated; and a control circuit configured to select an active group of said plurality of groups in response to one or more control signals, wherein said control circuit is implemented within said groups of memory cells.
Claim 2
Dependent Claim
75 words
A circuit comprising: a first and a second bitline each configured to read arid write data to one or more of a plurality of groups of memory cells, wherein each of said plurality of groups of memory cells is interdigitated; and a control circuit configured to select an active group of said plurality of groups in response to one or more control signals, wherein said control circuit is implemented within said groups of memory cells.
Claim 3
Dependent Claim
19 words
The circuit according to claim 1, wherein each of said groups of memory cells comprises a plurality of blocks.
Claim 4
Dependent Claim
19 words
The circuit according to claim 2, wherein each of said plurality of blocks comprises a plurality of short sub-wordlines.
Claim 5
Dependent Claim
26 words
The circuit according to claim 3, wherein each of said cells in said active group are active when said short sub-wordlines are active, without column addresses.
Claim 6
Dependent Claim
28 words
The circuit according to claim 1, wherein said control circuit further comprises a single address transition detection circuit configured to decode said data to be read or written.
Claim 7
Dependent Claim
21 words
The circuit according to claim 2, wherein each block of said plurality of blocks comprises a sub-wordline driver for each row.
Claim 8
Dependent Claim
15 words
The circuit according to claim 1, wherein said first and second bitline have cross-coupled loads.
Claim 9
Dependent Claim
47 words
The circuit according to claim 1, further comprising one or more local buses and one or more global buses, wherein each of said local buses comprises one or more single-ended local Q buses and each of said global buses comprises one or more single-ended global Q buses.
Claim 10
Dependent Claim
21 words
The circuit according to claim 2, wherein each block of said plurality of blocks comprises a plurality of said memory cells.
Claim 11
Dependent Claim
34 words
The circuit according to claim 8, where each of said first and second bitline pair comprises a sense amplifier, wherein said each sense amplifier is configured to drive said one or more local buses.
Claim 12
Dependent Claim
23 words
The circuit according to claim 2, wherein said control circuit is further configured to disconnect a defective block from a block power supply.
Claim 13
Dependent Claim
30 words
The circuit according to claim 11, wherein said control circuit is further configured to replace said defective block with one or more redundant blocks that are active only when enabled.
Claim 14
Dependent Claim
17 words
The circuit according to claim 1, wherein said plurality of groups are organized in rows and blocks.
Claim 15
Dependent Claim
38 words
A circuit comprising: means for reading and writing to and from a plurality of groups of interdigitated bitlines; and means for selecting an active group within said plurality of groups in response to one or more control signals.
Claim 16
Dependent Claim
38 words
A circuit comprising: means for reading and writing to and from a plurality of groups of interdigitated bitlines; and means for selecting an active group within said plurality of groups in response to one or more control signals.
Claim 17
Dependent Claim
18 words
The circuit according to claim 14, wherein said means for selecting comprise a single address transition detection signal.
Claim 18
Independent Claim
82 words
A method for reading and writing data to a plurality of memory cells comprising the steps of: (A) reading and writing to and/or from a selected group of a plurality of groups of said memory cells using a first and a second bitline; and (B) selecting said active group of said plurality of groups in response to one or more control signals, wherein said active group is selected in response to (i) a single address transition detection signal and (ii) an address.
Claim 19
Independent Claim
82 words
A method for reading and writing data to a plurality of memory cells comprising the steps of: (A) reading and writing to and/or from a selected group of a plurality of groups of said memory cells using a first and a second bitline; and (B) selecting said active group of said plurality of groups in response to one or more control signals, wherein said active group is selected in response to (i) a single address transition detection signal and (ii) an address.
Claim 20
Dependent Claim
21 words
The method according to claim 16, wherein each group is organized in a plurality of rows and a plurality of blocks.
Claim 21
Dependent Claim
22 words
The method according to claim 17, wherein each block of said plurality of blocks comprises a sub wordline driver for each row.
Claim 22
Dependent Claim
19 words
The method according to claim 18, wherein each of said first and second bitline pair comprises a sense amplifier.
Claim 23
Dependent Claim
35 words
The method according to claim 17 further comprising the following step: (C) disconnecting a defective block of said plurality of blocks from a block power supply and replacing the defective block with a redundant block.
References Cited (Backward Citations)
US5036491A
Cited
US5060200A
Cited
US4982372A
Cited
US5119334A
Cited
US4985639A
Cited
US5126973A
Cited
US5270975A
Cited
US5379257A
Cited
US5389828A
Cited
US5600274A
Cited
US5264745A
Cited
US5438550A
Cited
US5696463A
Cited
US5555529A
Cited
US5691933A
Cited
US5841687A
Cited
US5872464A
Cited
US5886937A
Cited
US5828614A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-19 | 2004-06-19 | 2004-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-19 | 2008-06-19 | 2008-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-19 | 2012-06-19 | 2012-12-19 | $7700.00 | Window Closed / Lapsed |