US6208545B1
Expired / Lapsed
US
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Three dimensional structure memory
Assignee: ELM 3DS INNOVATONS LLC
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Filing: 1997-11-17
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Granted: 2001-03-27
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Expires: 2017-11-17
Abstract
Abstract A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
Inventors
- 👤 Glenn J. Leedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:03
CPC Classifications
H; H10; H10D; H10D84/00; B; B44; B44C; B44C1/00; B44C1/22; G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/846; G11C5/00; G11C5/02; G11C5/025; G11C5/04; H10B; H10B12/00; H10B12/50; H10B99/00; H10D88/00; H10W; H10W20/00; H10W20/20; H10W70/00; H10W70/60; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G11C29/80; G11C29/81; G11C29/848; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/30; H10W72/351; H10W72/352; H10W90/00; H10W90/20; H10W90/297; Y; Y10; Y10S; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
99 words
A method of information processing using a stacked integrated circuit memory including a memory controller layer and multiple memory layers, the method comprising the steps of: initiating a memory access; and during the memory access, independently routing data vertically between the memory controller layer and selected storage locations within each of many memory blocks on a single memory layer, wherein said routing occurs through a dense output array interior to the stacked integrated circuit memory; and wherein during a single memory access cycle, many bytes of data are routed from the selected storage locations to the memory controller layer.
Claim 2
Independent Claim
99 words
A method of information processing using a stacked integrated circuit memory including a memory controller layer and multiple memory layers, the method comprising the steps of: initiating a memory access; and during the memory access, independently routing data vertically between the memory controller layer and selected storage locations within each of many memory blocks on a single memory layer, wherein said routing occurs through a dense output array interior to the stacked integrated circuit memory; and wherein during a single memory access cycle, many bytes of data are routed from the selected storage locations to the memory controller layer.
Claim 3
Independent Claim
96 words
A method of information processing using a stacked integrated circuit memory including a logic layer and multiple memory layers, the method comprising the steps of: initiating a memory access; and during the memory access, independently routing data vertically between the logic layer and selected storage locations within each of many memory blocks on a single memory layer, wherein said routing occurs through a dense output array interior to the stacked integrated circuit memory; and wherein during a single memory access cycle, many bytes of data are routed from the selected storage locations to the logic layer.
Claim 4
Independent Claim
96 words
A method of information processing using a stacked integrated circuit memory including a logic layer and multiple memory layers, the method comprising the steps of: initiating a memory access; and during the memory access, independently routing data vertically between the logic layer and selected storage locations within each of many memory blocks on a single memory layer, wherein said routing occurs through a dense output array interior to the stacked integrated circuit memory; and wherein during a single memory access cycle, many bytes of data are routed from the selected storage locations to the logic layer.
Claim 5
Dependent Claim
21 words
The method of claim 1 , comprising the further steps of: during simultaneous memory accesses, accessing data from multiple memory layers.
Claim 6
Dependent Claim
25 words
The method of claim 3 , wherein data from one memory layer is used instead of data from another memory layer having a defective portion.
Claim 7
Dependent Claim
26 words
The method of claim 3 , wherein data from one memory layer is used to perform ECC processing with respect to data from another memory layer.
Claim 8
Dependent Claim
44 words
The method of claim 2 , comprising the further steps of: receiving within the memory controller layer data from the selected storage locations; and for each selected storage location, distinguishing between at least four voltage levels to produce at least two bits of data.
Claim 9
Dependent Claim
22 words
The method of claim 2 , comprising the further steps of: receiving data within the memory controller layer; and decompressing the data.
Claim 10
Dependent Claim
27 words
The method of claim 2 , comprising the further steps of: compressing data within the memory controller layer; and writing the data to the selected memory locations.
Claim 11
Dependent Claim
24 words
The method of claim 2 , wherein the logic layer is a memory controller layer, further comprising memory circuits formed within said memory layers.
Claim 12
Dependent Claim
28 words
The method of claim 9 , comprising the further steps of: receiving within the logic layer a virtual address; and translating the virtual address to a real address.
Claim 13
Dependent Claim
28 words
The method of claim 9 , comprising the further steps of: receiving within the logic layer an indirect address; and translating the indirect address to an absolute address.
Claim 14
Dependent Claim
44 words
The method of claim 9 , wherein a memory circuit is a content-addressable memory circuit, comprising the further step of receiving within the logic layer a content word and producing as an output signal an address of the content word within the memory circuit.
Claim 15
Dependent Claim
34 words
The method of claim 2 , wherein said memory access is read access, comprising the further steps of subsequent to said read access performing one of audio encoding and audio decoding on said data.
Claim 16
Dependent Claim
34 words
The method of claim 2 , wherein said memory access is write access, comprising the further steps of prior to said write access performing one of audio encoding and audio decoding on said data.
Claim 17
Dependent Claim
34 words
The method of claim 2 , wherein said memory access is read access, comprising the further steps of subsequent to said read access performing one of video encoding and video decoding on said data.
Claim 18
Dependent Claim
34 words
The method of claim 2 , wherein said memory access is write access, comprising the further steps of prior to said write access performing one of video encoding and video decoding on said data.
Claim 19
Dependent Claim
29 words
The method of claim 2 , wherein said memory access is read access, comprising the further steps of subsequent to said read access performing recognition processing on said data.
Claim 20
Dependent Claim
29 words
The method of claim 2 , wherein said memory access is write access, comprising the further steps of prior to said write access performing recognition processing on said data.
Claim 21
Dependent Claim
14 words
The method of claim 17 , wherein said recognition processing is voice recognition processing.
Claim 22
Dependent Claim
14 words
The method of claim 17 , wherein said recognition processing is handwriting recognition processing.
Claim 23
Dependent Claim
13 words
The method of claim 18 wherein said recognition processing is voice recognition processing.
Claim 24
Dependent Claim
13 words
The method of claim 18 wherein said recognition processing is handwriting recognition processing.
Claim 25
Dependent Claim
19 words
The method of claim 2 , comprising the further step of performing power management functions within said logic layer.
Claim 26
Dependent Claim
19 words
The method of claim 2 , comprising the further step of performing graphics acceleration functions within said logic layer.
Claim 27
Dependent Claim
19 words
The method of claim 2 , comprising the further step of performing database processing functions within said logic layer.
Claim 28
Dependent Claim
13 words
The method of claim 2 , wherein said logic layer is a microprocessor.
Claim 29
Dependent Claim
29 words
The method of claim 9 , wherein said memory controller layer is fabricated using a semiconductor process technology, and said memory circuits are formed using a different process technology.
Claim 30
Dependent Claim
28 words
The method of claim 27 , wherein said different process technology is selected from a group consisting of: DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-26 | 2004-09-25 | 2005-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-26 | 2008-09-25 | 2009-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-26 | 2012-09-25 | 2013-03-27 | $7700.00 | Window Closed / Lapsed |